forked from Imagelibrary/rtems
465 lines
12 KiB
C
465 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSDeviceGRLIBSPICTRL
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*
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* @brief This header file defines the SPICTRL register block interface.
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*/
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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/* Generated from spec:/dev/grlib/if/spictrl-header */
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#ifndef _GRLIB_SPICTRL_REGS_H
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#define _GRLIB_SPICTRL_REGS_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Generated from spec:/dev/grlib/if/spictrl */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRL SPICTRL
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*
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* @ingroup RTEMSDeviceGRLIB
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*
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* @brief This group contains the SPICTRL interfaces.
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*
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* @{
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*/
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLCAP Capability register (CAP)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_CAP_SSSZ_SHIFT 24
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#define SPICTRL_CAP_SSSZ_MASK 0xff000000U
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#define SPICTRL_CAP_SSSZ_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_CAP_SSSZ_MASK ) >> \
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SPICTRL_CAP_SSSZ_SHIFT )
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#define SPICTRL_CAP_SSSZ_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_CAP_SSSZ_MASK ) | \
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( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \
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SPICTRL_CAP_SSSZ_MASK ) )
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#define SPICTRL_CAP_SSSZ( _val ) \
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( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \
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SPICTRL_CAP_SSSZ_MASK )
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#define SPICTRL_CAP_MAXWLEN_SHIFT 20
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#define SPICTRL_CAP_MAXWLEN_MASK 0xf00000U
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#define SPICTRL_CAP_MAXWLEN_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_CAP_MAXWLEN_MASK ) >> \
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SPICTRL_CAP_MAXWLEN_SHIFT )
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#define SPICTRL_CAP_MAXWLEN_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_CAP_MAXWLEN_MASK ) | \
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( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \
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SPICTRL_CAP_MAXWLEN_MASK ) )
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#define SPICTRL_CAP_MAXWLEN( _val ) \
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( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \
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SPICTRL_CAP_MAXWLEN_MASK )
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#define SPICTRL_CAP_TWEN 0x80000U
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#define SPICTRL_CAP_AMODE 0x40000U
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#define SPICTRL_CAP_ASELA 0x20000U
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#define SPICTRL_CAP_SSEN 0x10000U
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#define SPICTRL_CAP_FDEPTH_SHIFT 8
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#define SPICTRL_CAP_FDEPTH_MASK 0xff00U
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#define SPICTRL_CAP_FDEPTH_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_CAP_FDEPTH_MASK ) >> \
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SPICTRL_CAP_FDEPTH_SHIFT )
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#define SPICTRL_CAP_FDEPTH_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_CAP_FDEPTH_MASK ) | \
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( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \
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SPICTRL_CAP_FDEPTH_MASK ) )
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#define SPICTRL_CAP_FDEPTH( _val ) \
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( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \
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SPICTRL_CAP_FDEPTH_MASK )
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#define SPICTRL_CAP_SR 0x80U
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#define SPICTRL_CAP_FT_SHIFT 5
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#define SPICTRL_CAP_FT_MASK 0x60U
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#define SPICTRL_CAP_FT_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_CAP_FT_MASK ) >> \
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SPICTRL_CAP_FT_SHIFT )
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#define SPICTRL_CAP_FT_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_CAP_FT_MASK ) | \
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( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \
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SPICTRL_CAP_FT_MASK ) )
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#define SPICTRL_CAP_FT( _val ) \
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( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \
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SPICTRL_CAP_FT_MASK )
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#define SPICTRL_CAP_REV_SHIFT 0
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#define SPICTRL_CAP_REV_MASK 0x1fU
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#define SPICTRL_CAP_REV_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_CAP_REV_MASK ) >> \
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SPICTRL_CAP_REV_SHIFT )
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#define SPICTRL_CAP_REV_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_CAP_REV_MASK ) | \
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( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \
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SPICTRL_CAP_REV_MASK ) )
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#define SPICTRL_CAP_REV( _val ) \
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( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \
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SPICTRL_CAP_REV_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLMODE Mode register (MODE)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_MODE_LOOP 0x40000000U
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#define SPICTRL_MODE_CPOL 0x20000000U
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#define SPICTRL_MODE_CPHA 0x10000000U
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#define SPICTRL_MODE_DIV_16 0x8000000U
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#define SPICTRL_MODE_REV 0x4000000U
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#define SPICTRL_MODE_MX 0x2000000U
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#define SPICTRL_MODE_EN 0x1000000U
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#define SPICTRL_MODE_LEN_SHIFT 20
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#define SPICTRL_MODE_LEN_MASK 0xf00000U
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#define SPICTRL_MODE_LEN_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_MODE_LEN_MASK ) >> \
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SPICTRL_MODE_LEN_SHIFT )
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#define SPICTRL_MODE_LEN_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_MODE_LEN_MASK ) | \
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( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \
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SPICTRL_MODE_LEN_MASK ) )
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#define SPICTRL_MODE_LEN( _val ) \
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( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \
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SPICTRL_MODE_LEN_MASK )
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#define SPICTRL_MODE_PM_SHIFT 16
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#define SPICTRL_MODE_PM_MASK 0xf0000U
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#define SPICTRL_MODE_PM_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_MODE_PM_MASK ) >> \
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SPICTRL_MODE_PM_SHIFT )
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#define SPICTRL_MODE_PM_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_MODE_PM_MASK ) | \
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( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \
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SPICTRL_MODE_PM_MASK ) )
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#define SPICTRL_MODE_PM( _val ) \
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( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \
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SPICTRL_MODE_PM_MASK )
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#define SPICTRL_MODE_TWEN 0x8000U
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#define SPICTRL_MODE_ASEL 0x4000U
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#define SPICTRL_MODE_FACT 0x2000U
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#define SPICTRL_MODE_OD 0x1000U
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#define SPICTRL_MODE_CG_SHIFT 7
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#define SPICTRL_MODE_CG_MASK 0xf80U
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#define SPICTRL_MODE_CG_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_MODE_CG_MASK ) >> \
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SPICTRL_MODE_CG_SHIFT )
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#define SPICTRL_MODE_CG_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_MODE_CG_MASK ) | \
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( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \
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SPICTRL_MODE_CG_MASK ) )
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#define SPICTRL_MODE_CG( _val ) \
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( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \
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SPICTRL_MODE_CG_MASK )
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#define SPICTRL_MODE_ASELDEL_SHIFT 5
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#define SPICTRL_MODE_ASELDEL_MASK 0x60U
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#define SPICTRL_MODE_ASELDEL_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_MODE_ASELDEL_MASK ) >> \
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SPICTRL_MODE_ASELDEL_SHIFT )
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#define SPICTRL_MODE_ASELDEL_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_MODE_ASELDEL_MASK ) | \
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( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \
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SPICTRL_MODE_ASELDEL_MASK ) )
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#define SPICTRL_MODE_ASELDEL( _val ) \
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( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \
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SPICTRL_MODE_ASELDEL_MASK )
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#define SPICTRL_MODE_TAC 0x10U
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#define SPICTRL_MODE_TTO 0x8U
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#define SPICTRL_MODE_IGSEL 0x4U
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#define SPICTRL_MODE_CITE 0x2U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLEVENT Event register (EVENT)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_EVENT_TIP 0x80000000U
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#define SPICTRL_EVENT_LT 0x4000U
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#define SPICTRL_EVENT_OV 0x1000U
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#define SPICTRL_EVENT_UN 0x800U
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#define SPICTRL_EVENT_MME 0x400U
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#define SPICTRL_EVENT_NE 0x200U
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#define SPICTRL_EVENT_NF 0x100U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLMASK Mask register (MASK)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_MASK_TIPE 0x80000000U
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#define SPICTRL_MASK_LTE 0x4000U
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#define SPICTRL_MASK_OVE 0x1000U
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#define SPICTRL_MASK_UNE 0x800U
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#define SPICTRL_MASK_MMEE 0x400U
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#define SPICTRL_MASK_NEEE 0x200U
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#define SPICTRL_MASK_NFE 0x100U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLCMD Command register (CMD)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_CMD_LST 0x400000U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLTX Transmit register (TX)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_TX_TDATA_SHIFT 0
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#define SPICTRL_TX_TDATA_MASK 0xffffffffU
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#define SPICTRL_TX_TDATA_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_TX_TDATA_MASK ) >> \
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SPICTRL_TX_TDATA_SHIFT )
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#define SPICTRL_TX_TDATA_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_TX_TDATA_MASK ) | \
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( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \
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SPICTRL_TX_TDATA_MASK ) )
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#define SPICTRL_TX_TDATA( _val ) \
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( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \
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SPICTRL_TX_TDATA_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLRX Receive register (RX)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_RX_RDATA_SHIFT 0
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#define SPICTRL_RX_RDATA_MASK 0xffffffffU
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#define SPICTRL_RX_RDATA_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_RX_RDATA_MASK ) >> \
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SPICTRL_RX_RDATA_SHIFT )
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#define SPICTRL_RX_RDATA_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_RX_RDATA_MASK ) | \
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( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \
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SPICTRL_RX_RDATA_MASK ) )
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#define SPICTRL_RX_RDATA( _val ) \
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( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \
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SPICTRL_RX_RDATA_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLSLVSEL Slave select register (SLVSEL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_SLVSEL_SLVSEL_SHIFT 0
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#define SPICTRL_SLVSEL_SLVSEL_MASK 0x3U
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#define SPICTRL_SLVSEL_SLVSEL_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_SLVSEL_SLVSEL_MASK ) >> \
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SPICTRL_SLVSEL_SLVSEL_SHIFT )
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#define SPICTRL_SLVSEL_SLVSEL_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_SLVSEL_SLVSEL_MASK ) | \
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( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \
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SPICTRL_SLVSEL_SLVSEL_MASK ) )
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#define SPICTRL_SLVSEL_SLVSEL( _val ) \
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( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \
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SPICTRL_SLVSEL_SLVSEL_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBSPICTRLASLVSEL \
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* Automatic slave select register (ASLVSEL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define SPICTRL_ASLVSEL_ASLVSEL_SHIFT 0
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#define SPICTRL_ASLVSEL_ASLVSEL_MASK 0x3U
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#define SPICTRL_ASLVSEL_ASLVSEL_GET( _reg ) \
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( ( ( _reg ) & SPICTRL_ASLVSEL_ASLVSEL_MASK ) >> \
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SPICTRL_ASLVSEL_ASLVSEL_SHIFT )
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#define SPICTRL_ASLVSEL_ASLVSEL_SET( _reg, _val ) \
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( ( ( _reg ) & ~SPICTRL_ASLVSEL_ASLVSEL_MASK ) | \
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( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \
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SPICTRL_ASLVSEL_ASLVSEL_MASK ) )
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#define SPICTRL_ASLVSEL_ASLVSEL( _val ) \
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( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \
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SPICTRL_ASLVSEL_ASLVSEL_MASK )
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/** @} */
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/**
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* @brief This structure defines the SPICTRL register block memory map.
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*/
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typedef struct spictrl {
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLCAP.
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*/
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uint32_t cap;
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uint32_t reserved_4_20[ 7 ];
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLMODE.
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*/
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uint32_t mode;
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLEVENT.
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*/
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uint32_t event;
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLMASK.
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*/
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uint32_t mask;
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLCMD.
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*/
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uint32_t cmd;
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLTX.
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*/
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uint32_t tx;
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLRX.
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*/
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uint32_t rx;
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLSLVSEL.
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*/
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uint32_t slvsel;
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/**
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* @brief See @ref RTEMSDeviceGRLIBSPICTRLASLVSEL.
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*/
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uint32_t aslvsel;
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} spictrl;
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _GRLIB_SPICTRL_REGS_H */
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