forked from Imagelibrary/rtems
124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/**
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* @file
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*
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* @ingroup sparc_erc32
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*
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* @brief THARSYS VME SPARC RT board SONIC Configuration Information
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*
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* References:
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*
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* 1) SVME/DMV-171 Single Board Computer Documentation Package, #805905,
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* DY 4 Systems Inc., Kanata, Ontario, September, 1996.
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*/
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/*
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* COPYRIGHT (c) 2000.
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* European Space Agency.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#define __INSIDE_RTEMS_BSD_TCPIP_STACK__
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#include <bsp.h>
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#include <libchip/sonic.h>
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#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
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#include <stdio.h>
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#endif
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static void erc32_sonic_write_register(
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void *base,
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uint32_t regno,
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uint32_t value
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)
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{
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volatile uint32_t *p = base;
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#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
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printf( "%p Write 0x%04x to %s (0x%02x)\n",
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&p[regno], value, SONIC_Reg_name[regno], regno );
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fflush( stdout );
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#endif
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p[regno] = 0x0ffff & value;
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}
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static uint32_t erc32_sonic_read_register(
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void *base,
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uint32_t regno
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)
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{
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volatile uint32_t *p = base;
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uint32_t value;
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value = p[regno];
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#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
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printf( "%p Read 0x%04x from %s (0x%02x)\n",
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&p[regno], value, SONIC_Reg_name[regno], regno );
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fflush( stdout );
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#endif
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return 0x0ffff & value;
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}
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/*
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* Default sizes of transmit and receive descriptor areas
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*/
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#define RDA_COUNT 20 /* 20 */
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#define TDA_COUNT 20 /* 10 */
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/*
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* Default device configuration register values
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* Conservative, generic values.
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* DCR:
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* No extended bus mode
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* Unlatched bus retry
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* Programmable outputs unused
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* Asynchronous bus mode
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* User definable pins unused
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* No wait states (access time controlled by DTACK*)
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* 32-bit DMA
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* Empty/Fill DMA mode
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* Maximum Transmit/Receive FIFO
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* DC2:
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* Extended programmable outputs unused
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* Normal HOLD request
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* Packet compress output unused
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* No reject on CAM match
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*/
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#define SONIC_DCR ( DCR_DW32 | DCR_RFT24 | DCR_TFT28)
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#define SONIC_DC2 (0)
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/*
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* Default location of device registers
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*/
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#define SONIC_BASE_ADDRESS 0x10000100
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/*
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* Default interrupt vector
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*/
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#define SONIC_VECTOR 0x1E
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sonic_configuration_t erc32_sonic_configuration = {
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(void *)SONIC_BASE_ADDRESS, /* base address */
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SONIC_VECTOR, /* vector number */
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SONIC_DCR, /* DCR register value */
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SONIC_DC2, /* DC2 register value */
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TDA_COUNT, /* number of transmit descriptors */
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RDA_COUNT, /* number of receive descriptors */
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erc32_sonic_write_register,
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erc32_sonic_read_register
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};
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int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config)
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{
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ERC32_MEC.IO_Configuration |=
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(0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8));
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ERC32_MEC.Control &= ~0x60001; /* Disable DMA time-out, parity & power-down */
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ERC32_MEC.Control |= 0x10000; /* Enable DMA */
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ERC32_MEC.Interrupt_Mask &= ~(1 << (SONIC_VECTOR - 0x10));
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return(rtems_sonic_driver_attach( config, &erc32_sonic_configuration ));
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}
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