forked from Imagelibrary/rtems
188 lines
5.9 KiB
C
188 lines
5.9 KiB
C
/**
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* @file
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* @ingroup mips_regs
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* @brief Standard MIPS register names.
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*/
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/*
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* regs.S -- standard MIPS register names.
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*
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* Copyright (c) 1995 Cygnus Support
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/**
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* @defgroup mips_regs MIPS Registers
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* @ingroup RTEMSBSPsMIPSShared
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* @brief MIPS Registers
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* @{
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*/
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/**
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* @name Standard MIPS register names:
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* @{
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*/
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#define zero $0
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#define z0 $0
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#define v0 $2
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#define v1 $3
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#define a0 $4
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#define a1 $5
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#define a2 $6
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#define a3 $7
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#define t0 $8
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define s0 $16
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#define s1 $17
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#define s2 $18
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#define s3 $19
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#define s4 $20
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#define s5 $21
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#define s6 $22
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#define s7 $23
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#define t8 $24
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#define t9 $25
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#define k0 $26 ///< @brief kernel private register 0 */
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#define k1 $27 ///< @brief kernel private register 1 */
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#define gp $28 ///< @brief global data pointer */
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#define sp $29 ///< @brief stack-pointer */
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#define fp $30 ///< @brief frame-pointer */
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#define ra $31 ///< @brief return address */
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#define pc $pc ///< @brief pc, used on mips16 */
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#define fp0 $f0
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#define fp1 $f1
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/** @} */
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/**
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* @name Useful memory constants:
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* @{
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*/
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#define K0BASE 0x80000000
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#ifndef __mips64
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#define K1BASE 0xA0000000
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#else
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#define K1BASE 0xFFFFFFFFA0000000LL
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#endif
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/** @} */
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#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
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/**
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* @name Standard Co-Processor 0 register numbers:
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* @{
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*/
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#define C0_COUNT $9 ///< @brief Count Register */
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#define C0_SR $12 ///< @brief Status Register */
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#define C0_CAUSE $13 ///< @brief last exception description */
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#define C0_EPC $14 ///< @brief Exception error address */
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#define C0_CONFIG $16 ///< @brief CPU configuration */
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/** @} */
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/**
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* @name Standard Status Register bitmasks:
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* @{
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*/
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#define SR_CU1 0x20000000 ///< @brief Mark CP1 as usable */
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#define SR_FR 0x04000000 ///< @brief Enable MIPS III FP registers */
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#define SR_BEV 0x00400000 ///< @brief Controls location of exception vectors */
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#define SR_PE 0x00100000 ///< @brief Mark soft reset (clear parity error) */
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#define SR_KX 0x00000080 ///< @brief Kernel extended addressing enabled */
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#define SR_SX 0x00000040 ///< @brief Supervisor extended addressing enabled */
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#define SR_UX 0x00000020 ///< @brief User extended addressing enabled */
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/** @} */
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/**
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* @name Standard (R4000) cache operations.
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* @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition:
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* @{
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*/
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#define CACHE_I (0) ///< @brief primary instruction */
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#define CACHE_D (1) ///< @brief primary data */
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#define CACHE_SI (2) ///< @brief secondary instruction */
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#define CACHE_SD (3) ///< @brief secondary data (or combined instruction/data) */
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#define INDEX_INVALIDATE (0) ///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */
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#define INDEX_LOAD_TAG (1)
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#define INDEX_STORE_TAG (2)
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#define CREATE_DIRTY_EXCLUSIVE (3) ///< @brief CACHE_D and CACHE_SD only */
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#define HIT_INVALIDATE (4)
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#define CACHE_FILL (5) ///< @brief CACHE_I only */
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#define HIT_WRITEBACK_INVALIDATE (5) ///< @brief CACHE_D and CACHE_SD only */
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#define HIT_WRITEBACK (6) ///< @brief CACHE_I, CACHE_D and CACHE_SD only */
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#define HIT_SET_VIRTUAL (7) ///< @brief CACHE_SI and CACHE_SD only */
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#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
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/** @} */
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/**
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* @name Individual cache operations:
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* @{
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*/
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#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
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#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
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#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
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#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
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#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
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#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
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#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
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#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
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#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
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#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
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#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
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#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
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#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
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#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
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#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
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#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
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#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
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#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
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#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
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#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
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#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
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#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
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#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
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#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
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#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
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#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
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/** @} */
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/** @} */
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/*> EOF regs.S <*/
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