forked from Imagelibrary/rtems
4cf93658ef
The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
144 lines
3.1 KiB
C
144 lines
3.1 KiB
C
/**
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* @file
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*
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* Cache Management Support Routines for the MCF532x
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*/
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#include <rtems.h>
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#include <mcf532x/mcf532x.h>
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#include "cache.h"
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#define m68k_set_cacr(_cacr) \
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__asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
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/*
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* Read/write copy of common cache
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* Default cache mode is *disabled* (cache only ACRx areas)
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* Allow CPUSHL to invalidate a cache line
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* Enable store buffer
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*/
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static uint32_t cacr_mode = MCF_CACR_ESB |
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MCF_CACR_DCM(3);
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/*
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* Cannot be frozen
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*/
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static void _CPU_cache_freeze_data(void)
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{
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}
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static void _CPU_cache_unfreeze_data(void)
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{
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}
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static void _CPU_cache_freeze_instruction(void)
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{
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}
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static void _CPU_cache_unfreeze_instruction(void)
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{
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}
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static void _CPU_cache_flush_1_data_line(const void *d_addr)
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{
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register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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}
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static void _CPU_cache_flush_entire_data(void)
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{
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register unsigned long set, adr;
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for(set = 0; set < 256; ++set) {
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adr = (set << 4);
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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}
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}
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static void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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if(!(cacr_mode & MCF_CACR_CENB))
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{
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cacr_mode |= MCF_CACR_CENB;
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m68k_set_cacr(cacr_mode);
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}
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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if((cacr_mode & MCF_CACR_CENB))
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{
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cacr_mode &= ~MCF_CACR_CENB;
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m68k_set_cacr(cacr_mode);
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}
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_invalidate_entire_instruction(void)
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{
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m68k_set_cacr(cacr_mode | MCF_CACR_CINVA);
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}
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static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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adr += 1;
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
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}
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static void _CPU_cache_enable_data(void)
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{
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/*
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* The 532x has a unified data and instruction cache, so we call through
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* to enable instruction.
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*/
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_CPU_cache_enable_instruction();
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}
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static void _CPU_cache_disable_data(void)
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{
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/*
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* The 532x has a unified data and instruction cache, so we call through
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* to disable instruction.
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*/
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_CPU_cache_disable_instruction();
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}
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static void _CPU_cache_invalidate_entire_data(void)
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{
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_CPU_cache_invalidate_entire_instruction();
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}
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static void _CPU_cache_invalidate_1_data_line(const void *addr)
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{
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_CPU_cache_invalidate_1_instruction_line(addr);
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}
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#include "../../../shared/cache/cacheimpl.h"
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