forked from Imagelibrary/rtems
69ed59f083
* bootloader/misc.c, console/Makefile.am, console/console.c, console/consoleIo.h, console/inch.c, console/polled_io.c, console/uart.c, console/uart.h, include/bsp.h, irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_init.c, openpic/openpic.c, openpic/openpic.h, pci/Makefile.am, pci/pci.c, pci/pci.h, residual/Makefile.am, start/start.S, startup/bspstart.c, vectors/vectors.S, vectors/vectors.h, vectors/vectors_init.c: Per PR216, "libbsp/powerpc/shared" BSP has been modified considerably with the goal to make it more flexible and reusable by other BSPs. The main strategies were: - eliminate hardcoded base addresses; devices use offsets and a BSP defined base address. - separate functionality into different files (e.g. reboot from inch.c to reboot.c) which can be overridden by a 'derived' BSP. - separate initialization code into separate files (e.g. PCI bridge detection/initialization was separated from the more generic PCI access routines), also to make it easier for 'derived' BSPs to substitute their own initialization code. There are also a couple of enhancements and fixes: - IRQ handling code now has a hook for attaching a VME bridge. - OpenPIC is now explicitely initialized (polarities, senses). Eliminated the implicit assumption on the presence of an ISA PIC. - UART and console driver now supports more than 1 port. The current maximum of 2 can easily be extended by enlarging a table (it would even be easier if the ISR API was not broken by design). - fixed polled_io.c so it correctly supports console on COM2 - fixed TLB invalidation code (start.S). - exception handler prints a stack backtrace. - added BSP_pciFindDevice() to scan the pci bus for a particular vendor/device/instance.
303 lines
8.4 KiB
C
303 lines
8.4 KiB
C
/*
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* pci.c : this file contains basic PCI Io functions.
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*
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* CopyRight (C) 1999 valette@crf.canon.fr
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*
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* This code is heavilly inspired by the public specification of STREAM V2
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* that can be found at :
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*
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* <http://www.chorus.com/Documentation/index.html> by following
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* the STREAM API Specification Document link.
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*
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* Till Straumann, <strauman@slac.stanford.edu>, 1/2002
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* - separated bridge detection code out of this file
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*/
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#include <libcpu/io.h>
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#include <bsp/pci.h>
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/* allow for overriding these definitions */
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#ifndef PCI_CONFIG_ADDR
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#define PCI_CONFIG_ADDR 0xcf8
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#endif
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#ifndef PCI_CONFIG_DATA
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#define PCI_CONFIG_DATA 0xcfc
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#endif
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#define PCI_INVALID_VENDORDEVICEID 0xffffffff
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#define PCI_MULTI_FUNCTION 0x80
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/* define a shortcut */
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#define pci BSP_pci_configuration
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/*
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* Bit encode for PCI_CONFIG_HEADER_TYPE register
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*/
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unsigned char ucMaxPCIBus;
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static int
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indirect_pci_read_config_byte(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned char *val) {
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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*val = in_8(pci.pci_config_data + (offset&3));
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_pci_read_config_word(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned short *val) {
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*val = 0xffff;
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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*val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)));
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_pci_read_config_dword(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned int *val) {
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*val = 0xffffffff;
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
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*val = in_le32((volatile unsigned int *)pci.pci_config_data);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_pci_write_config_byte(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned char val) {
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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out_8(pci.pci_config_data + (offset&3), val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_pci_write_config_word(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned short val) {
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_pci_write_config_dword(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned int val) {
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
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out_le32((volatile unsigned int *)pci.pci_config_data, val);
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return PCIBIOS_SUCCESSFUL;
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}
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const pci_config_access_functions pci_indirect_functions = {
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indirect_pci_read_config_byte,
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indirect_pci_read_config_word,
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indirect_pci_read_config_dword,
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indirect_pci_write_config_byte,
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indirect_pci_write_config_word,
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indirect_pci_write_config_dword
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};
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pci_config BSP_pci_configuration = {(volatile unsigned char*)PCI_CONFIG_ADDR,
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(volatile unsigned char*)PCI_CONFIG_DATA,
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&pci_indirect_functions};
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static int
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direct_pci_read_config_byte(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned char *val) {
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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*val=0xff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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*val=in_8(pci.pci_config_data + ((1<<slot)&~1)
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+ (function<<8) + offset);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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direct_pci_read_config_word(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned short *val) {
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*val = 0xffff;
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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*val=in_le16((volatile unsigned short *)
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(pci.pci_config_data + ((1<<slot)&~1)
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+ (function<<8) + offset));
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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direct_pci_read_config_dword(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned int *val) {
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*val = 0xffffffff;
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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*val=in_le32((volatile unsigned int *)
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(pci.pci_config_data + ((1<<slot)&~1)
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+ (function<<8) + offset));
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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direct_pci_write_config_byte(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned char val) {
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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out_8(pci.pci_config_data + ((1<<slot)&~1)
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+ (function<<8) + offset,
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val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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direct_pci_write_config_word(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned short val) {
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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out_le16((volatile unsigned short *)
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(pci.pci_config_data + ((1<<slot)&~1)
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+ (function<<8) + offset),
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val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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direct_pci_write_config_dword(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char offset, unsigned int val) {
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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out_le32((volatile unsigned int *)
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(pci.pci_config_data + ((1<<slot)&~1)
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+ (function<<8) + offset),
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val);
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return PCIBIOS_SUCCESSFUL;
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}
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const pci_config_access_functions pci_direct_functions = {
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direct_pci_read_config_byte,
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direct_pci_read_config_word,
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direct_pci_read_config_dword,
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direct_pci_write_config_byte,
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direct_pci_write_config_word,
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direct_pci_write_config_dword
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};
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/*
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* This routine determines the maximum bus number in the system
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*/
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void InitializePCI()
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{
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extern void detect_host_bridge();
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unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs;
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unsigned char ucHeader;
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unsigned char ucMaxSubordinate;
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unsigned int ulClass, ulDeviceID;
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detect_host_bridge();
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/*
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* Scan PCI bus 0 looking for PCI-PCI bridges
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*/
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for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) {
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(void)pci_read_config_dword(0,
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ucSlotNumber,
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0,
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PCI_VENDOR_ID,
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&ulDeviceID);
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if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
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/*
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* This slot is empty
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*/
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continue;
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}
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(void)pci_read_config_byte(0,
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ucSlotNumber,
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0,
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PCI_HEADER_TYPE,
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&ucHeader);
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if(ucHeader&PCI_MULTI_FUNCTION) {
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ucNumFuncs=PCI_MAX_FUNCTIONS;
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}
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else {
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ucNumFuncs=1;
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}
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for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) {
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(void)pci_read_config_dword(0,
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ucSlotNumber,
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ucFnNumber,
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PCI_VENDOR_ID,
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&ulDeviceID);
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if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
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/*
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* This slot/function is empty
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*/
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continue;
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}
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/*
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* This slot/function has a device fitted.
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*/
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(void)pci_read_config_dword(0,
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ucSlotNumber,
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ucFnNumber,
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PCI_CLASS_REVISION,
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&ulClass);
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ulClass >>= 16;
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if (ulClass == PCI_CLASS_BRIDGE_PCI) {
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/*
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* We have found a PCI-PCI bridge
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*/
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(void)pci_read_config_byte(0,
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ucSlotNumber,
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ucFnNumber,
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PCI_SUBORDINATE_BUS,
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&ucMaxSubordinate);
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if(ucMaxSubordinate>ucMaxPCIBus) {
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ucMaxPCIBus=ucMaxSubordinate;
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}
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}
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}
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}
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}
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/*
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* Return the number of PCI busses in the system
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*/
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unsigned char BusCountPCI()
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{
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return(ucMaxPCIBus+1);
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}
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