forked from Imagelibrary/rtems
dddbdf4d9a
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to emphasize that this BSP is for the lock-step mode RPU configuration. Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split mode RPU configuration for core 0 and 1 respectively.
21 lines
502 B
YAML
21 lines
502 B
YAML
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
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actions:
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- get-integer: null
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- format-and-define: null
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build-type: option
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copyrights:
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- Copyright (C) 2024 embedded brains GmbH & Co. KG
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default:
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- enabled-by: ZYNQMP_RPU_SPLIT_INDEX_1
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value: 0xff110004
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- enabled-by: true
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value: 0xff110000
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description: |
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This option defines the Xilinx Triple-Timer Counter (TTC) base address used by
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the Clock Driver.
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enabled-by: true
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format: '{:#010x}'
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links: []
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name: XIL_CLOCK_TTC_BASE_ADDR
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type: build
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