forked from Imagelibrary/rtems
ab8817ca03
Add directives to get and set the priority of an interrupt vector. Implement the directives for the following BSP families: * arm/lpc24xx * arm/lpc32xx * powerpc/mpc55xxevb * powerpc/qoriq Implement the directives for the following interrupt controllers: * GICv2 and GICv3 (arm and aarch64) * NVIC (arm) * PLIC (riscv) Update #5002.
82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup DevIRQGIC
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*
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* @brief This source file contains the implementation of
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* bsp_interrupt_get_attributes() for the GICv2 of Xilinx Zynq UltraScale+
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* MPSoC and RFSoC devices.
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*/
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/*
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* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
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* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dev/irq/arm-gic.h>
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#include <bsp/irq-generic.h>
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rtems_status_code bsp_interrupt_get_attributes(
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rtems_vector_number vector,
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rtems_interrupt_attributes *attributes
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)
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{
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attributes->is_maskable = true;
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attributes->maybe_enable = true;
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attributes->maybe_disable = true;
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attributes->can_raise = true;
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attributes->can_get_priority = true;
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attributes->can_set_priority = true;
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attributes->maximum_priority = 255;
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if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
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/*
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* It is implementation-defined whether implemented SGIs are permanently
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* enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
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* GICD_ICENABLER0.
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*/
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attributes->can_raise_on = true;
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attributes->cleared_by_acknowledge = true;
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attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
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} else {
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attributes->can_disable = true;
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attributes->can_clear = true;
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attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
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/*
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* Interrupt 67 affinity value presents as unimplemented in the
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* configuration of the GICv2 instance used in ZynqMP CPUs.
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*/
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if ( vector > ARM_GIC_IRQ_PPI_LAST && vector != 67 ) {
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/* SPI */
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attributes->can_get_affinity = true;
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attributes->can_set_affinity = true;
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}
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}
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return RTEMS_SUCCESSFUL;
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}
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