forked from Imagelibrary/rtems
dddbdf4d9a
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to emphasize that this BSP is for the lock-step mode RPU configuration. Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split mode RPU configuration for core 0 and 1 respectively.
226 lines
6.9 KiB
C
226 lines
6.9 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSDriverClockXilTTC
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*
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* @brief This source file contains a Clock Driver implementation using the
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* Xilinx Triple Timer Counter (TTC).
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*/
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/*
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* Copyright (C) 2024 embedded brains GmbH & Co. KG
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* Copyright (C) 2023 Reflex Aerospace GmbH
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*
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* Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp.h>
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#include <bsp/irq-generic.h>
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#include <bsp/fatal.h>
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#include <dev/clock/xttcps_hw.h>
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#include <rtems/sysinit.h>
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#include <rtems/timecounter.h>
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#include <rtems/score/processormaskimpl.h>
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#if XTTCPS_COUNT_VALUE_MASK != UINT32_MAX
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#error "unexpected XTTCPS_COUNT_VALUE_MASK value"
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#endif
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/**
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* @defgroup RTEMSDriverClockXilTTC \
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* Xilinx Triple Timer Counter (TTC) Clock Driver
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*
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* @ingroup RTEMSDriverClockImpl
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*
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* @brief This group contains the Xilinx Triple Timer Counter (TTC) Clock
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* Driver implementation.
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*
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* @{
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*/
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uint32_t _CPU_Counter_frequency( void )
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{
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return XIL_CLOCK_TTC_REFERENCE_CLOCK;
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}
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CPU_Counter_ticks _CPU_Counter_read(void)
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{
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return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
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}
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static void xil_ttc_initialize(void)
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{
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/* Do not use a prescaler to get a high resolution time source */
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XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CLK_CNTRL_OFFSET, 0);
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/* Disable interupts */
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XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET, 0);
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/*
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* Enable the timer, do not enable waveform output, increment up, use
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* overflow mode, enable match mode.
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*/
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XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CNT_CNTRL_OFFSET,
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XTTCPS_CNT_CNTRL_EN_WAVE_MASK | XTTCPS_CNT_CNTRL_MATCH_MASK);
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}
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RTEMS_SYSINIT_ITEM(
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xil_ttc_initialize,
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RTEMS_SYSINIT_CPU_COUNTER,
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RTEMS_SYSINIT_ORDER_MIDDLE
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);
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typedef struct {
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struct timecounter base;
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uint32_t irq_match_interval;
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} xil_ttc_timecounter;
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static xil_ttc_timecounter xil_ttc_clock_instance;
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static uint32_t xil_ttc_get_timecount(struct timecounter *tc)
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{
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(void) tc;
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return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
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}
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static void xil_ttc_clock_driver_support_initialize_hardware(void)
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{
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xil_ttc_timecounter *tc;
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uint64_t frequency;
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uint32_t irq_match_interval;
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uint32_t count;
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tc = &xil_ttc_clock_instance;
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frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK;
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irq_match_interval = (uint32_t)
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((frequency * rtems_configuration_get_microseconds_per_tick()) / 1000000);
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/* Setup match register to generate clock interrupts */
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count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
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XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET,
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count + irq_match_interval);
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/* Clear interupts (clear on read) */
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(void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
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/* Enable interupt for match register */
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XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET,
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XTTCPS_IXR_MATCH_0_MASK);
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/* Install timecounter */
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tc->irq_match_interval = irq_match_interval;
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tc->base.tc_counter_mask = UINT32_MAX;
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tc->base.tc_frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK;
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tc->base.tc_get_timecount = xil_ttc_get_timecount;
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tc->base.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
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rtems_timecounter_install(&tc->base);
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}
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static void xil_ttc_clock_driver_support_at_tick(xil_ttc_timecounter *tc)
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{
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uint32_t irq_match_interval;
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uint32_t count;
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uint32_t match;
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irq_match_interval = tc->irq_match_interval;
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/* Update match register */
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match = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET);
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match += irq_match_interval;
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XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match);
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/* Clear interupts (clear on read) */
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(void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
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/* Check that the new match value is in the future */
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count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
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while (RTEMS_PREDICT_FALSE(match - count > irq_match_interval)) {
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/*
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* Tick misses may happen if interrupts are disabled for an extremly long
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* period or while debugging.
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*/
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rtems_timecounter_tick();
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/* Update match register */
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match += irq_match_interval;
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XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match);
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/* Clear interupts (clear on read) */
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(void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
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/* Maybe the new match value is now in the future */
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count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
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}
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}
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static rtems_interrupt_entry xil_ttc_interrupt_entry;
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static void xil_ttc_clock_driver_support_install_isr(
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rtems_interrupt_handler handler
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)
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{
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rtems_status_code sc;
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#if !defined(ZYNQMP_RPU_LOCK_STEP_MODE) && ZYNQMP_RPU_SPLIT_INDEX != 0
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Processor_mask affinity;
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_Processor_mask_From_uint32_t(
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&affinity,
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UINT32_C(1) << ZYNQMP_RPU_SPLIT_INDEX,
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0
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);
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(void) bsp_interrupt_set_affinity(XIL_CLOCK_TTC_IRQ, &affinity);
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#endif
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rtems_interrupt_entry_initialize(
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&xil_ttc_interrupt_entry,
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handler,
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&xil_ttc_clock_instance,
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"Clock"
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);
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sc = rtems_interrupt_entry_install(
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XIL_CLOCK_TTC_IRQ,
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RTEMS_INTERRUPT_UNIQUE,
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&xil_ttc_interrupt_entry
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);
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if ( sc != RTEMS_SUCCESSFUL ) {
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bsp_fatal(XIL_FATAL_TTC_IRQ_INSTALL);
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}
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}
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#define Clock_driver_support_at_tick(arg) \
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xil_ttc_clock_driver_support_at_tick(arg)
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#define Clock_driver_support_initialize_hardware \
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xil_ttc_clock_driver_support_initialize_hardware
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#define Clock_driver_support_install_isr(isr) \
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xil_ttc_clock_driver_support_install_isr(isr)
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/** @} */
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#include "../../../shared/dev/clock/clockimpl.h"
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