forked from Imagelibrary/rtems
- Change mvme2100 to mot_pcc_mvme2100 to avoid clashing with the RTEMS_BSP value for the BSP. You cannot have a define that is the BSP name.
198 lines
6.2 KiB
C
198 lines
6.2 KiB
C
#include <libcpu/io.h>
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#include <libcpu/spr.h>
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#include <inttypes.h>
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#include <bsp.h>
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#include <bsp/pci.h>
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#include <bsp/consoleIo.h>
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#include <bsp/residual.h>
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#include <bsp/openpic.h>
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#include <bsp/irq.h>
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#include <rtems/bspIo.h>
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#include <libcpu/cpuIdent.h>
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#define SHOW_RAVEN_SETTINGS
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#define RAVEN_MPIC_IOSPACE_ENABLE 0x0001
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#define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
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#define RAVEN_MASTER_ENABLE 0x0004
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#define RAVEN_PARITY_CHECK_ENABLE 0x0040
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#define RAVEN_SYSTEM_ERROR_ENABLE 0x0100
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#define RAVEN_CLEAR_EVENTS_MASK 0xf9000000
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#define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020)
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#define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024)
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#define MEREN_VAL 0x2f00
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#define pci BSP_pci_configuration
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extern const pci_config_access_functions pci_direct_functions;
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extern const pci_config_access_functions pci_indirect_functions;
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#if defined(mot_ppc_mvme2100)
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/* FIXME - this should really be in a separate file - the 2100 doesn't
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* have a raven chip so there is no point having 2100 code here
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*/
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extern unsigned int EUMBBAR;
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void detect_host_bridge(void)
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{
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/*
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* If the processor is an 8240 or an 8245 then the PIC is built
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* in instead of being on the PCI bus. The MVME2100 is using Processor
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* Address Map B (CHRP) although the Programmer's Reference Guide says
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* it defaults to Map A.
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*/
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/* We have an EPIC Interrupt Controller */
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OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
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pci.pci_functions = &pci_indirect_functions;
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pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
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pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
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}
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#else
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#if 0
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/* Unfortunately, PCI config space access to empty slots generates
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* a 'signalled master abort' condition --> we can't really use
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* the machine check interrupt for memory probing unless
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* we use probing for PCI scanning also (which would make
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* all that code either BSP dependent or requiring yet another
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* API, sigh...).
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* So for the moment, we just don't use MCP on all mvme2xxx
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* boards (using the generic, hostbridge-independent 'clear'
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* implementation [generic_clear_hberrs.c]).
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*/
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/*
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* enableMCP: whether to enable MCP checkstop / machine check interrupts
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* on the hostbridge and in HID0.
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*
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* NOTE: HID0 and MEREN are left alone if this flag is 0
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*
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* quiet : be silent
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*
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* RETURNS : raven MERST register contents (lowermost 16 bits), 0 if
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* there were no errors
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*/
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unsigned long
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_BSP_clear_hostbridge_errors(int enableMCP, int quiet)
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{
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unsigned merst;
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merst = in_be32(RAVEN_MPIC_MERST);
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/* write back value to clear status */
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out_be32(RAVEN_MPIC_MERST, merst);
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if (enableMCP) {
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if (!quiet)
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printk("Enabling MCP generation on hostbridge errors\n");
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out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
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} else {
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out_be32(RAVEN_MPIC_MEREN, 0);
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if ( !quiet && enableMCP ) {
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printk("leaving MCP interrupt disabled\n");
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}
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}
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return (merst & 0xffff);
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}
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#endif
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void detect_host_bridge(void)
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{
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PPC_DEVICE *hostbridge;
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uint32_t id0;
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uint32_t tmp;
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/*
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* This code assumes that the host bridge is located at
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* bus 0, dev 0, func 0 AND that the old pre PCI 2.1
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* standard devices detection mechanism that was used on PC
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* (still used in BSD source code) works.
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*/
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hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
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BridgeController,
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PCIBridge, -1, 0);
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if (hostbridge) {
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if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
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pci.pci_functions=&pci_indirect_functions;
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/* Should be extracted from residual data,
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* indeed MPC106 in CHRP mode is different,
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* but we should not use residual data in
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* this case anyway.
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*/
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pci.pci_config_addr = ((volatile unsigned char *)
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(ptr_mem_map->io_base+0xcf8));
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pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
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} else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
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pci.pci_functions=&pci_direct_functions;
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pci.pci_config_data=(unsigned char *) 0x80800000;
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} else {
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}
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} else {
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/* Let us try by experimentation at our own risk! */
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pci.pci_functions = &pci_direct_functions;
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/* On all direct bridges I know the host bridge itself
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* appears as device 0 function 0.
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*/
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pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
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if (id0==~0U) {
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pci.pci_functions = &pci_indirect_functions;
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pci.pci_config_addr = ((volatile unsigned char*)
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(ptr_mem_map->io_base+0xcf8));
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pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
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}
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/* Here we should check that the host bridge is actually
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* present, but if it not, we are in such a desperate
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* situation, that we probably can't even tell it.
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*/
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}
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pci_read_config_dword(0, 0, 0, 0, &id0);
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#ifdef SHOW_RAVEN_SETTINGS
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printk("idreg 0 = 0x%" PRIu32 "\n",id0);
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#endif
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if((id0 == PCI_VENDOR_ID_MOTOROLA +
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(PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) ||
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(id0 == PCI_VENDOR_ID_MOTOROLA +
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(PCI_DEVICE_ID_MOTOROLA_HAWK<<16))) {
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/*
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* We have a Raven bridge. We will get information about its settings
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*/
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pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
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#ifdef SHOW_RAVEN_SETTING
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printk("RAVEN PCI command register = %x\n",id0);
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#endif
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id0 |= RAVEN_CLEAR_EVENTS_MASK;
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pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
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pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
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#ifdef SHOW_RAVEN_SETTING
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printk("After error clearing RAVEN PCI command register = %x\n",id0);
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#endif
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if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
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pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
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#ifdef SHOW_RAVEN_SETTING
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printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
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#endif
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}
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if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
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pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
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#ifdef SHOW_RAVEN_SETTING
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printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
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#endif
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OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
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printk("OpenPIC found at %p.\n", OpenPIC);
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}
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}
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#if BSP_PCI_IRQ_NUMBER > 0
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if (OpenPIC == (volatile struct OpenPIC *)0) {
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rtems_panic("OpenPic Not found\n");
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}
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#endif
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}
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#endif
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