forked from Imagelibrary/rtems
133 lines
3.8 KiB
C
133 lines
3.8 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* This set of routines starts the application. It includes application,
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* board, and monitor specific initialization and configuration.
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* The generic CPU dependent initialization has been performed
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* before any of these are invoked.
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*
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* COPYRIGHT (c) 1989-2008.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#include <fcntl.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <psim.h>
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#include <bsp/bootcard.h>
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#include <bsp/linker-symbols.h>
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#include <rtems/bspIo.h>
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#include <rtems/counter.h>
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#include <rtems/powerpc/powerpc.h>
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#include <libcpu/cpuIdent.h>
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#include <libcpu/bat.h>
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#include <libcpu/spr.h>
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SPR_RW(SPRG1)
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/* On psim, each click of the decrementer register corresponds
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* to 1 instruction. By setting this to 100, we are indicating
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* that we are assuming it can execute 100 instructions per
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* microsecond. This corresponds to sustaining 1 instruction
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* per cycle at 100 Mhz. Whether this is a good guess or not
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* is anyone's guess.
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*/
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extern int PSIM_INSTRUCTIONS_PER_MICROSECOND[];
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/*
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* PCI Bus Frequency
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*/
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unsigned int BSP_bus_frequency;
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/*
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* Driver configuration parameters
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*/
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uint32_t bsp_clicks_per_usec;
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/*
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* Memory on this board.
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*/
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uint32_t BSP_mem_size = (uint32_t)RamSize;
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/*
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* Time base divisior (how many tick for 1 second).
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*/
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unsigned int BSP_time_base_divisor;
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extern unsigned long __rtems_end[];
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uint32_t _CPU_Counter_frequency(void)
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{
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return bsp_clicks_per_usec * 1000000;
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}
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/*
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* bsp_start
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*
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* This routine does the bulk of the system initialization.
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*/
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void bsp_start( void )
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{
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/*
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* Note we can not get CPU identification dynamically.
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* PVR has to be set to PPC_PSIM (0xfffe) from the device
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* file.
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*/
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get_ppc_cpu_type();
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/*
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* initialize the device driver parameters
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*/
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BSP_bus_frequency = (unsigned int)PSIM_INSTRUCTIONS_PER_MICROSECOND;
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bsp_clicks_per_usec = BSP_bus_frequency;
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BSP_time_base_divisor = 1;
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ppc_exc_initialize_with_vector_base(
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(uintptr_t) _ISR_Stack_area_begin,
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(void *) 0xfff00000
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);
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/*
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* Initalize RTEMS IRQ system
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*/
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BSP_rtems_irq_mng_init(0);
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/*
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* Setup BATs and enable MMU
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*/
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/* Memory */
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setdbat(0, 0x0<<28, 0x0<<28, 1<<28, _PAGE_RW);
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setibat(0, 0x0<<28, 0x0<<28, 1<<28, 0);
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/* PCI */
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setdbat(1, 0x08<<24, 0x08<<24, 1<<24, IO_PAGE);
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setdbat(2, 0xfc<<24, 0xfc<<24, 1<<24, IO_PAGE);
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_write_MSR(_read_MSR() | MSR_DR | MSR_IR);
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__asm__ volatile("sync; isync");
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}
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