forked from Imagelibrary/rtems
9964895866
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
389 lines
9.4 KiB
ArmAsm
389 lines
9.4 KiB
ArmAsm
/*
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Based upon IDT provided code with the following release:
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This source code has been made available to you by IDT on an AS-IS
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basis. Anyone receiving this source is licensed under IDT copyrights
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to use it in any way he or she deems fit, including copying it,
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modifying it, compiling it, and redistributing it either with or
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without modifications. No license under IDT patents or patent
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applications is to be implied by the copyright license.
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Any user of this software should understand that IDT cannot provide
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technical support for this software and will not be responsible for
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any consequences resulting from the use of this software.
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Any person who transfers this source code or any derivative work must
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include the IDT copyright notice, this paragraph, and the preceeding
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two paragraphs in the transferred software.
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COPYRIGHT IDT CORPORATION 1996
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LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
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*/
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/*
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** idttlb.s - fetch the registers associated with and the contents
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** of the tlb.
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**
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*/
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/* 950308: Ketan patched a few tlb functions that would not have worked.*/
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#include <rtems/mips/iregdef.h>
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#include <rtems/mips/idtcpu.h>
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#include <rtems/asm.h>
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.text
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#if __mips == 1
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/*
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** ret_tlblo -- returns the 'entrylo' contents for the TLB
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** 'c' callable - as ret_tlblo(index) - where index is the
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** tlb entry to return the lo value for - if called from assembly
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** language then index should be in register a0.
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*/
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FRAME(ret_tlblo,sp,0,ra)
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.set noreorder
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mfc0 t0,C0_SR # save sr
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nop
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and t0,~SR_PE # dont inadvertantly clear PE
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mtc0 zero,C0_SR # clear interrupts
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mfc0 t1,C0_TLBHI # save pid
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sll a0,TLBINX_INXSHIFT # position index
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mtc0 a0,C0_INX # write to index register
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nop
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tlbr # put tlb entry in entrylo and hi
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nop
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mfc0 v0,C0_TLBLO # get the requested entry lo
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mtc0 t1,C0_TLBHI # restore pid
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mtc0 t0,C0_SR # restore status register
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j ra
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nop
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.set reorder
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ENDFRAME(ret_tlblo)
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#endif
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#if __mips == 3
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/*
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** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB
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** 'c' callable - as ret_tlblo(index) - where index is the
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** tlb entry to return the lo value for - if called from assembly
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** language then index should be in register a0.
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*/
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FRAME(ret_tlblo0,sp,0,ra)
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mfc0 t0,C0_SR # save sr
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mtc0 zero,C0_SR # clear interrupts
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mfc0 t1,C0_TLBHI # save pid
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mtc0 a0,C0_INX # write to index register
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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tlbr # put tlb entry in entrylo and hi
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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mfc0 v0,C0_TLBLO0 # get the requested entry lo
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mtc0 t1,C0_TLBHI # restore pid
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mtc0 t0,C0_SR # restore status register
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j ra
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ENDFRAME(ret_tlblo0)
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FRAME(ret_tlblo1,sp,0,ra)
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mfc0 t0,C0_SR # save sr
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mtc0 zero,C0_SR # clear interrupts
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mfc0 t1,C0_TLBHI # save pid
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mtc0 a0,C0_INX # write to index register
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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tlbr # put tlb entry in entrylo and hi
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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mfc0 v0,C0_TLBLO1 # get the requested entry lo
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mtc0 t1,C0_TLBHI # restore pid
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mtc0 t0,C0_SR # restore status register
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j ra
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ENDFRAME(ret_tlblo1)
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/*
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** ret_pagemask(index) -- return pagemask contents of tlb entry "index"
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*/
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FRAME(ret_pagemask,sp,0,ra)
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mfc0 t0,C0_SR # save sr
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mtc0 zero,C0_SR # disable interrupts
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mfc0 t1,C0_TLBHI # save current pid
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mtc0 a0,C0_INX # drop it in C0 register
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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tlbr # read entry to entry hi/lo
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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mfc0 v0,C0_PAGEMASK # to return value
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mtc0 t1,C0_TLBHI # restore current pid
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mtc0 t0,C0_SR # restore sr
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j ra
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ENDFRAME(ret_pagemask)
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/*
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** ret_tlbwired(void) -- return wired register
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*/
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FRAME(ret_tlbwired,sp,0,ra)
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mfc0 v0,C0_WIRED
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j ra
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ENDFRAME(ret_tlbwired)
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#endif
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/*
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** ret_tlbhi -- return the tlb entry high content for tlb entry
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** index
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*/
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FRAME(ret_tlbhi,sp,0,ra)
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#if __mips == 1
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.set noreorder
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mfc0 t0,C0_SR # save sr
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nop
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and t0,~SR_PE
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mtc0 zero,C0_SR # disable interrupts
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mfc0 t1,C0_TLBHI # save current pid
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sll a0,TLBINX_INXSHIFT # position index
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mtc0 a0,C0_INX # drop it in C0 register
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nop
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tlbr # read entry to entry hi/lo
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nop
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mfc0 v0,C0_TLBHI # to return value
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mtc0 t1,C0_TLBHI # restore current pid
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mtc0 t0,C0_SR # restore sr
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j ra
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nop
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.set reorder
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#endif
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#if __mips == 3
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mfc0 t0,C0_SR # save sr
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mtc0 zero,C0_SR # disable interrupts
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mfc0 t1,C0_TLBHI # save current pid
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mtc0 a0,C0_INX # drop it in C0 register
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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tlbr # read entry to entry hi/lo0/lo1/mask
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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mfc0 v0,C0_TLBHI # to return value
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mtc0 t1,C0_TLBHI # restore current pid
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mtc0 t0,C0_SR # restore sr
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j ra
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#endif
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ENDFRAME(ret_tlbhi)
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/*
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** ret_tlbpid() -- return tlb pid contained in the current entry hi
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*/
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FRAME(ret_tlbpid,sp,0,ra)
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#if __mips == 1
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.set noreorder
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mfc0 v0,C0_TLBHI # fetch tlb high
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nop
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and v0,TLBHI_PIDMASK # isolate and position
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srl v0,TLBHI_PIDSHIFT
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j ra
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nop
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.set reorder
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#endif
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#if __mips == 3
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mfc0 v0,C0_TLBHI # to return value
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nop
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and v0,TLBHI_PIDMASK
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j ra
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#endif
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ENDFRAME(ret_tlbpid)
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/*
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** tlbprobe(address, pid) -- probe the tlb to see if address is currently
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** mapped
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** a0 = vpn - virtual page numbers are 0=0 1=0x1000, 2=0x2000...
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** virtual page numbers for the r3000 are in
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** entry hi bits 31-12
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** a1 = pid - this is a process id ranging from 0 to 63
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** this process id is shifted left 6 bits and or'ed into
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** the entry hi register
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** returns an index value (0-63) if successful -1 -f not
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*/
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FRAME(tlbprobe,sp,0,ra)
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#if __mips == 1
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.set noreorder
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mfc0 t0,C0_SR /* fetch status reg */
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and a0,TLBHI_VPNMASK /* isolate just the vpn */
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and t0,~SR_PE /* don't inadvertantly clear pe */
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mtc0 zero,C0_SR
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mfc0 t1,C0_TLBHI
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sll a1,TLBHI_PIDSHIFT /* possition the pid */
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and a1,TLBHI_PIDMASK
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or a0,a1 /* build entry hi value */
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mtc0 a0,C0_TLBHI
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nop
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tlbp /* do the probe */
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nop
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mfc0 v1,C0_INX
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li v0,-1
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bltz v1,1f
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nop
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sra v0,v1,TLBINX_INXSHIFT /* get index positioned for return */
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1:
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mtc0 t1,C0_TLBHI /* restore tlb hi */
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mtc0 t0,C0_SR /* restore the status reg */
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j ra
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nop
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.set reorder
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#endif
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#if __mips == 3
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mfc0 t0,C0_SR # save sr
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mtc0 zero,C0_SR # disable interrupts
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mfc0 t1,C0_TLBHI # save current pid
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and a0,TLBHI_VPN2MASK # construct tlbhi for probe
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and a1,TLBHI_PIDMASK
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or a0,a1
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mtc0 a0,C0_TLBHI
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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tlbp # probe entry to entry hi/lo0/lo1/mask
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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mfc0 v1,C0_INX
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li v0,-1
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bltz v1,1f
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move v0,v1
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1: mtc0 t1,C0_TLBHI # restore current pid
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mtc0 t0,C0_SR # restore sr
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j ra
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#endif
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ENDFRAME(tlbprobe)
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/*
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** resettlb(index) Invalidate the TLB entry specified by index
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*/
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FRAME(resettlb,sp,0,ra)
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#if __mips == 1
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.set noreorder
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mfc0 t0,C0_TLBHI # fetch the current hi
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mfc0 v0,C0_SR # fetch the status reg.
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li t2,K0BASE&TLBHI_VPNMASK
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and v0,~SR_PE # dont inadvertantly clear PE
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mtc0 zero,C0_SR
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mtc0 t2,C0_TLBHI # set up tlbhi
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mtc0 zero,C0_TLBLO
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sll a0,TLBINX_INXSHIFT
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mtc0 a0,C0_INX
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nop
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tlbwi # do actual invalidate
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nop
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mtc0 t0,C0_TLBHI
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mtc0 v0,C0_SR
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j ra
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nop
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.set reorder
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#endif
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#if __mips == 3
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li t2,K0BASE&TLBHI_VPN2MASK
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mfc0 t0,C0_TLBHI # save current TLBHI
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mfc0 v0,C0_SR # save SR and disable interrupts
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mtc0 zero,C0_SR
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mtc0 t2,C0_TLBHI # invalidate entry
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mtc0 zero,C0_TLBLO0
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mtc0 zero,C0_TLBLO1
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mtc0 a0,C0_INX
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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tlbwi
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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mtc0 t0,C0_TLBHI
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mtc0 v0,C0_SR
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j ra
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#endif
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ENDFRAME(resettlb)
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#if __mips == 1
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/*
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** Setup TLB entry
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**
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** map_tlb(index, tlbhi, phypage)
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** a0 = TLB entry index
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** a1 = virtual page number and PID
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** a2 = physical page
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*/
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FRAME(map_tlb,sp,0,ra)
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.set noreorder
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sll a0,TLBINX_INXSHIFT
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mfc0 v0,C0_SR # fetch the current status
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mfc0 a3,C0_TLBHI # save the current hi
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and v0,~SR_PE # dont inadvertantly clear parity
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mtc0 zero,C0_SR
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mtc0 a1,C0_TLBHI # set the hi entry
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mtc0 a2,C0_TLBLO # set the lo entry
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mtc0 a0,C0_INX # load the index
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nop
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tlbwi # put the hi/lo in tlb entry indexed
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nop
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mtc0 a3,C0_TLBHI # put back the tlb hi reg
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mtc0 v0,C0_SR # restore the status register
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j ra
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nop
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.set reorder
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ENDFRAME(map_tlb)
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#endif
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#if __mips == 3
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/*
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** Setup R4000 TLB entry
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**
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** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd)
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** a0 = TLB entry index and page mask
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** a1 = virtual page number and PID
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** a2 = pte -- contents of even pte
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** a3 = pte -- contents of odd pte
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*/
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FRAME(map_tlb4000,sp,0,ra)
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and t2,a0,TLBPGMASK_MASK
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and a0,TLBINX_INXMASK
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mfc0 t1,C0_TLBHI # save current TLBPID
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mfc0 v0,C0_SR # save SR and disable interrupts
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mtc0 zero,C0_SR
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mtc0 t2,C0_PAGEMASK # set
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mtc0 a1,C0_TLBHI # set VPN and TLBPID
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mtc0 a2,C0_TLBLO0 # set PPN and access bits
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mtc0 a3,C0_TLBLO1 # set PPN and access bits
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mtc0 a0,C0_INX # set INDEX to wired entry
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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tlbwi # drop it in
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.set noreorder
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nop; nop; nop; nop; nop; nop; nop; nop
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.set reorder
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mtc0 t1,C0_TLBHI # restore TLBPID
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mtc0 v0,C0_SR # restore SR
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j ra
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ENDFRAME(map_tlb4000)
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#endif
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/*
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** Set current TLBPID. This assumes PID is positioned correctly in reg.
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** a0.
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*/
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FRAME(set_tlbpid,sp,0,ra)
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.set noreorder
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mtc0 a0,C0_TLBHI
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j ra
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nop
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.set reorder
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ENDFRAME(set_tlbpid)
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