forked from Imagelibrary/rtems
126 lines
3.2 KiB
ArmAsm
126 lines
3.2 KiB
ArmAsm
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* This file contains the raw entry points for the exceptions.
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*
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* COPYRIGHT (c) 1989-2000.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems/asm.h>
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#include <rtems/mips/iregdef.h>
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#include <rtems/mips/idtcpu.h>
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/*
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* MIPS ISA Level 1 entries
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*/
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#if __mips == 1
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FRAME(exc_norm_code,sp,0,ra)
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la k0, _ISR_Handler /* generic external int hndlr */
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j k0
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nop
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ENDFRAME(exc_norm_code)
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FRAME(exc_dbg_code,sp,0,ra)
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la k0, _DBG_Handler /* debug interrupt */
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j k0
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nop
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ENDFRAME(exc_dbg_code)
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/* XXX this is dependent on IDT/SIM and needs to be addressed */
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FRAME(exc_utlb_code,sp,0,ra)
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la k0, (R_VEC+((48)*8))
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j k0
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nop
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ENDFRAME(exc_utlb_code)
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/*
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* MIPS ISA Level 32
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* XXX Again, reliance on SIM. Not good.??????????
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*/
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#elif __mips == 32
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FRAME(exc_tlb_code,sp,0,ra)
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la k0, _ISR_Handler
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j k0
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nop
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ENDFRAME(exc_tlb_code)
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FRAME(exc_xtlb_code,sp,0,ra)
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la k0, _ISR_Handler
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j k0
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nop
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ENDFRAME(exc_xtlb_code)
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FRAME(exc_cache_code,sp,0,ra)
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la k0, _ISR_Handler
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j k0
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nop
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ENDFRAME(exc_cache_code)
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FRAME(exc_norm_code,sp,0,ra)
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la k0, _ISR_Handler /* generic external int hndlr */
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j k0
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nop
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ENDFRAME(exc_norm_code)
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/*
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* MIPS ISA Level 3
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* XXX Again, reliance on SIM. Not good.
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*/
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#elif __mips == 3
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FRAME(exc_tlb_code,sp,0,ra)
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la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
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j k0
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nop
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ENDFRAME(exc_tlb_code)
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FRAME(exc_xtlb_code,sp,0,ra)
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la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
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j k0
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nop
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ENDFRAME(exc_xtlb_code)
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FRAME(exc_cache_code,sp,0,ra)
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la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
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j k0
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nop
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ENDFRAME(exc_cache_code)
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FRAME(exc_norm_code,sp,0,ra)
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la k0, _ISR_Handler /* generic external int hndlr */
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j k0
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nop
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ENDFRAME(exc_norm_code)
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#else
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#error "isr_entries.S: ISA support problem"
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#endif
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