forked from Imagelibrary/rtems
0149e6e749
Updates the recently merged relicensed files with the 2-Clause BSD SPDX annotation. Closes #5208.
465 lines
17 KiB
C
465 lines
17 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* AMD AU1X00 specific information
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*/
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/*
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* Copyright (C) 2005 by Cogent Computer Systems
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* Written by Jay Monkman <jtm@lopingdog.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __AU1X00_H__
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#define __AU1X00_H__
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#define bit(x) (1 << (x))
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/* Au1x00 CP0 registers
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*/
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#define CP0_Index $0
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#define CP0_Random $1
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#define CP0_EntryLo0 $2
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#define CP0_EntryLo1 $3
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#define CP0_Context $4
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#define CP0_PageMask $5
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#define CP0_Wired $6
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#define CP0_BadVAddr $8
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#define CP0_Count $9
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#define CP0_EntryHi $10
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#define CP0_Compare $11
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#define CP0_Status $12
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#define CP0_Cause $13
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#define CP0_EPC $14
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#define CP0_PRId $15
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#define CP0_Config $16
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#define CP0_Config0 $16
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#define CP0_Config1 $16,1
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#define CP0_LLAddr $17
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#define CP0_WatchLo $18
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#define CP0_IWatchLo $18,1
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#define CP0_WatchHi $19
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#define CP0_IWatchHi $19,1
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#define CP0_Scratch $22
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#define CP0_Debug $23
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#define CP0_DEPC $24
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#define CP0_PerfCnt $25
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#define CP0_PerfCtrl $25,1
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#define CP0_DTag $28
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#define CP0_DData $28,1
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#define CP0_ITag $29
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#define CP0_IData $29,1
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#define CP0_ErrorEPC $30
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#define CP0_DESave $31
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/* Addresses common to all AU1x00 CPUs */
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#define AU1X00_MEM_ADDR 0xB4000000
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#define AU1X00_AC97_ADDR 0xB0000000
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#define AU1X00_USBH_ADDR 0xB0100000
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#define AU1X00_USBD_ADDR 0xB0200000
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#define AU1X00_MACDMA0_ADDR 0xB4004000
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#define AU1X00_MACDMA1_ADDR 0xB4004200
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#define AU1X00_UART0_ADDR 0xB1100000
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#define AU1X00_UART3_ADDR 0xB1400000
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#define AU1X00_SYS_ADDR 0xB1900000
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#define AU1X00_GPIO2_ADDR 0xB1700000
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#define AU1X00_IC0_ADDR 0xB0400000
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#define AU1X00_IC1_ADDR 0xB1800000
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/* Au1100 base addresses (in KSEG1 region) */
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#define AU1100_MAC0_ADDR 0xB0500000
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#define AU1100_MACEN_ADDR 0xB0520000
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/* Au1500 base addresses (in KSEG1 region) */
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#define AU1500_MAC0_ADDR 0xB1500000
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#define AU1500_MAC1_ADDR 0xB1510000
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#define AU1500_MACEN_ADDR 0xB1520000
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#define AU1500_PCI_ADDR 0xB4005000
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/* Au1x00 gpio2 register offsets
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*/
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#define gpio2_dir 0x0000
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#define gpio2_output 0x0008
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#define gpio2_pinstate 0x000c
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#define gpio2_inten 0x0010
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#define gpio2_enable 0x0014
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/* Au1x00 memory controller register offsets
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*/
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#define mem_sdmode0 0x0000
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#define mem_sdmode1 0x0004
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#define mem_sdmode2 0x0008
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#define mem_sdaddr0 0x000C
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#define mem_sdaddr1 0x0010
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#define mem_sdaddr2 0x0014
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#define mem_sdrefcfg 0x0018
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#define mem_sdprecmd 0x001C
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#define mem_sdautoref 0x0020
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#define mem_sdwrmd0 0x0024
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#define mem_sdwrmd1 0x0028
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#define mem_sdwrmd2 0x002C
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#define mem_sdsleep 0x0030
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#define mem_sdsmcke 0x0034
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#define mem_stcfg0 0x1000
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#define mem_sttime0 0x1004
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#define mem_staddr0 0x1008
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#define mem_stcfg1 0x1010
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#define mem_sttime1 0x1014
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#define mem_staddr1 0x1018
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#define mem_stcfg2 0x1020
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#define mem_sttime2 0x1024
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#define mem_staddr2 0x1028
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#define mem_stcfg3 0x1030
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#define mem_sttime3 0x1034
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#define mem_staddr3 0x1038
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/*
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* Au1x00 peripheral register offsets
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*/
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#define ac97_enable 0x0010
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#define usbh_enable 0x0007FFFC
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#define usbd_enable 0x0058
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#define irda_enable 0x0040
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#define macen_mac0 0x0000
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#define macen_mac1 0x0004
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#define i2s_enable 0x0008
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#define uart_enable 0x0100
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#define ssi_enable 0x0100
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#define sys_scratch0 0x0018
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#define sys_scratch1 0x001c
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#define sys_cntctrl 0x0014
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#define sys_freqctrl0 0x0020
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#define sys_freqctrl1 0x0024
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#define sys_clksrc 0x0028
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#define sys_pinfunc 0x002C
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#define sys_powerctrl 0x003C
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#define sys_endian 0x0038
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#define sys_wakesrc 0x005C
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#define sys_cpupll 0x0060
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#define sys_auxpll 0x0064
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#define sys_pininputen 0x0110
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#define pci_cmem 0x0000
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#define pci_config 0x0004
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#define pci_b2bmask_cch 0x0008
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#define pci_b2bbase0_venid 0x000C
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#define pci_b2bbase1_id 0x0010
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#define pci_mwmask_dev 0x0014
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#define pci_mwbase_rev_ccl 0x0018
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#define pci_err_addr 0x001C
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#define pci_spec_intack 0x0020
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#define pci_id 0x0100
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#define pci_statcmd 0x0104
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#define pci_classrev 0x0108
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#define pci_hdrtype 0x010C
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#define pci_mbar 0x0110
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/*
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* CSB250-specific values
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*/
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#define SYS_CPUPLL 33
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#define SYS_POWERCTRL 1
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#define SYS_AUXPLL 8
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#define SYS_CNTCTRL 256
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/* RCE0: */
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#define MEM_STCFG0 0x00000203
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#define MEM_STTIME0 0x22080b20
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#define MEM_STADDR0 0x11f03fc0
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/* RCE1: */
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#define MEM_STCFG1 0x00000203
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#define MEM_STTIME1 0x22080b20
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#define MEM_STADDR1 0x11e03fc0
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/* RCE2: */
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#define MEM_STCFG2 0x00000244
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#define MEM_STTIME2 0x22080a20
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#define MEM_STADDR2 0x11803f00
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/* RCE3: */
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#define MEM_STCFG3 0x00000201
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#define MEM_STTIME3 0x22080b20
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#define MEM_STADDR3 0x11003f00
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/*
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* SDCS0 -
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* SDCS1 -
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* SDCS2 -
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*/
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#define MEM_SDMODE0 0x00552229
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#define MEM_SDMODE1 0x00552229
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#define MEM_SDMODE2 0x00552229
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#define MEM_SDADDR0 0x001003F8
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#define MEM_SDADDR1 0x001023F8
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#define MEM_SDADDR2 0x001043F8
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#define MEM_SDREFCFG_D 0x74000c30 /* disable */
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#define MEM_SDREFCFG_E 0x76000c30 /* enable */
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#define MEM_SDWRMD0 0x00000023
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#define MEM_SDWRMD1 0x00000023
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#define MEM_SDWRMD2 0x00000023
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#define MEM_1MS ((396000000/1000000) * 1000)
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#define AU1X00_IC_CFG0RD(x) (*(volatile uint32_t*)(x + 0x40))
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#define AU1X00_IC_CFG0SET(x) (*(volatile uint32_t*)(x + 0x40))
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#define AU1X00_IC_CFG0CLR(x) (*(volatile uint32_t*)(x + 0x44))
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#define AU1X00_IC_CFG1RD(x) (*(volatile uint32_t*)(x + 0x48))
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#define AU1X00_IC_CFG1SET(x) (*(volatile uint32_t*)(x + 0x48))
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#define AU1X00_IC_CFG1CLR(x) (*(volatile uint32_t*)(x + 0x4c))
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#define AU1X00_IC_CFG2RD(x) (*(volatile uint32_t*)(x + 0x50))
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#define AU1X00_IC_CFG2SET(x) (*(volatile uint32_t*)(x + 0x50))
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#define AU1X00_IC_CFG2CLR(x) (*(volatile uint32_t*)(x + 0x54))
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#define AU1X00_IC_REQ0INT(x) (*(volatile uint32_t*)(x + 0x54))
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#define AU1X00_IC_SRCRD(x) (*(volatile uint32_t*)(x + 0x58))
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#define AU1X00_IC_SRCSET(x) (*(volatile uint32_t*)(x + 0x58))
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#define AU1X00_IC_SRCCLR(x) (*(volatile uint32_t*)(x + 0x5c))
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#define AU1X00_IC_REQ1INT(x) (*(volatile uint32_t*)(x + 0x5c))
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#define AU1X00_IC_ASSIGNRD(x) (*(volatile uint32_t*)(x + 0x60))
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#define AU1X00_IC_ASSIGNSET(x) (*(volatile uint32_t*)(x + 0x60))
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#define AU1X00_IC_ASSIGNCLR(x) (*(volatile uint32_t*)(x + 0x64))
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#define AU1X00_IC_WAKERD(x) (*(volatile uint32_t*)(x + 0x68))
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#define AU1X00_IC_WAKESET(x) (*(volatile uint32_t*)(x + 0x68))
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#define AU1X00_IC_WAKECLR(x) (*(volatile uint32_t*)(x + 0x6c))
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#define AU1X00_IC_MASKRD(x) (*(volatile uint32_t*)(x + 0x70))
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#define AU1X00_IC_MASKSET(x) (*(volatile uint32_t*)(x + 0x70))
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#define AU1X00_IC_MASKCLR(x) (*(volatile uint32_t*)(x + 0x74))
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#define AU1X00_IC_RISINGRD(x) (*(volatile uint32_t*)(x + 0x78))
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#define AU1X00_IC_RISINGCLR(x) (*(volatile uint32_t*)(x + 0x78))
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#define AU1X00_IC_FALLINGRD(x) (*(volatile uint32_t*)(x + 0x7c))
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#define AU1X00_IC_FALLINGCLR(x) (*(volatile uint32_t*)(x + 0x7c))
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#define AU1X00_IC_TESTBIT(x) (*(volatile uint32_t*)(x + 0x80))
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#define AU1X00_IC_IRQ_MAC0 (bit(28))
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#define AU1X00_IC_IRQ_MAC1 (bit(29))
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#define AU1X00_IC_IRQ_TOY_MATCH0 (bit(15))
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#define AU1X00_IC_IRQ_TOY_MATCH1 (bit(16))
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#define AU1X00_IC_IRQ_TOY_MATCH2 (bit(17))
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#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00))
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#define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04))
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#define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08))
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#define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c))
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#define AU1X00_SYS_TOYMATCH2(x) (*(volatile uint32_t*)(x + 0x10))
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#define AU1X00_SYS_CNTCTRL(x) (*(volatile uint32_t*)(x + 0x14))
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#define AU1X00_SYS_SCRATCH0(x) (*(volatile uint32_t*)(x + 0x18))
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#define AU1X00_SYS_SCRATCH1(x) (*(volatile uint32_t*)(x + 0x1c))
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#define AU1X00_SYS_WAKEMSK(x) (*(volatile uint32_t*)(x + 0x34))
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#define AU1X00_SYS_ENDIAN(x) (*(volatile uint32_t*)(x + 0x38))
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#define AU1X00_SYS_POWERCTRL(x) (*(volatile uint32_t*)(x + 0x3c))
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#define AU1X00_SYS_TOYREAD(x) (*(volatile uint32_t*)(x + 0x40))
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#define AU1X00_SYS_RTCTRIM(x) (*(volatile uint32_t*)(x + 0x44))
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#define AU1X00_SYS_RTCWRITE(x) (*(volatile uint32_t*)(x + 0x48))
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#define AU1X00_SYS_RTCMATCH0(x) (*(volatile uint32_t*)(x + 0x4c))
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#define AU1X00_SYS_RTCMATCH1(x) (*(volatile uint32_t*)(x + 0x50))
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#define AU1X00_SYS_RTCMATCH2(x) (*(volatile uint32_t*)(x + 0x54))
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#define AU1X00_SYS_RTCREAD(x) (*(volatile uint32_t*)(x + 0x58))
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#define AU1X00_SYS_WAKESRC(x) (*(volatile uint32_t*)(x + 0x5c))
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#define AU1X00_SYS_SLPPWR(x) (*(volatile uint32_t*)(x + 0x78))
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#define AU1X00_SYS_SLEEP(x) (*(volatile uint32_t*)(x + 0x7c))
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#define AU1X00_SYS_CNTCTRL_ERS (bit(23))
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#define AU1X00_SYS_CNTCTRL_RTS (bit(20))
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#define AU1X00_SYS_CNTCTRL_RM2 (bit(19))
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#define AU1X00_SYS_CNTCTRL_RM1 (bit(18))
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#define AU1X00_SYS_CNTCTRL_RM0 (bit(17))
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#define AU1X00_SYS_CNTCTRL_RS (bit(16))
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#define AU1X00_SYS_CNTCTRL_BP (bit(14))
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#define AU1X00_SYS_CNTCTRL_REN (bit(13))
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#define AU1X00_SYS_CNTCTRL_BRT (bit(12))
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#define AU1X00_SYS_CNTCTRL_TEN (bit(11))
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#define AU1X00_SYS_CNTCTRL_BTT (bit(10))
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#define AU1X00_SYS_CNTCTRL_E0 (bit(8))
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#define AU1X00_SYS_CNTCTRL_ETS (bit(7))
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#define AU1X00_SYS_CNTCTRL_32S (bit(5))
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#define AU1X00_SYS_CNTCTRL_TTS (bit(4))
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#define AU1X00_SYS_CNTCTRL_TM2 (bit(3))
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#define AU1X00_SYS_CNTCTRL_TM1 (bit(2))
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#define AU1X00_SYS_CNTCTRL_TM0 (bit(1))
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#define AU1X00_SYS_CNTCTRL_TS (bit(0))
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#define AU1X00_SYS_WAKEMSK_M20 (bit(8))
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#define AU1X00_MAC_CONTROL(x) (*(volatile uint32_t*)(x + 0x00))
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#define AU1X00_MAC_ADDRHIGH(x) (*(volatile uint32_t*)(x + 0x04))
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#define AU1X00_MAC_ADDRLOW(x) (*(volatile uint32_t*)(x + 0x08))
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#define AU1X00_MAC_HASHHIGH(x) (*(volatile uint32_t*)(x + 0x0c))
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#define AU1X00_MAC_HASHLOW(x) (*(volatile uint32_t*)(x + 0x10))
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#define AU1X00_MAC_MIICTRL(x) (*(volatile uint32_t*)(x + 0x14))
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#define AU1X00_MAC_MIIDATA(x) (*(volatile uint32_t*)(x + 0x18))
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#define AU1X00_MAC_FLOWCTRL(x) (*(volatile uint32_t*)(x + 0x1c))
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#define AU1X00_MAC_VLAN1(x) (*(volatile uint32_t*)(x + 0x20))
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#define AU1X00_MAC_VLAN2(x) (*(volatile uint32_t*)(x + 0x24))
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#define AU1X00_MAC_EN0 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x0))
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#define AU1X00_MAC_EN1 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x4))
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#define AU1X00_MAC_DMA_TX0_ADDR(x) (*(volatile uint32_t*)(x + 0x000))
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#define AU1X00_MAC_DMA_TX1_ADDR(x) (*(volatile uint32_t*)(x + 0x010))
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#define AU1X00_MAC_DMA_TX2_ADDR(x) (*(volatile uint32_t*)(x + 0x020))
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#define AU1X00_MAC_DMA_TX3_ADDR(x) (*(volatile uint32_t*)(x + 0x030))
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#define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile uint32_t*)(x + 0x100))
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#define AU1X00_MAC_DMA_RX1_ADDR(x) (*(volatile uint32_t*)(x + 0x110))
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#define AU1X00_MAC_DMA_RX2_ADDR(x) (*(volatile uint32_t*)(x + 0x120))
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#define AU1X00_MAC_DMA_RX3_ADDR(x) (*(volatile uint32_t*)(x + 0x130))
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typedef struct {
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volatile uint32_t stat;
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volatile uint32_t addr;
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uint32_t _rsv0;
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uint32_t _rsv1;
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} au1x00_macdma_rx_t;
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typedef struct {
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volatile uint32_t stat;
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volatile uint32_t addr;
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volatile uint32_t len;
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uint32_t _rsv0;
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} au1x00_macdma_tx_t;
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#define AU1X00_MAC_CTRL_RA (bit(31))
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#define AU1X00_MAC_CTRL_EM (bit(30))
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#define AU1X00_MAC_CTRL_DO (bit(23))
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#define AU1X00_MAC_CTRL_LM(x) ((x) << 21)
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#define AU1X00_MAC_CTRL_LM_NORMAL ((0) << 21)
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#define AU1X00_MAC_CTRL_LM_INTERNAL ((1) << 21)
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#define AU1X00_MAC_CTRL_LM_EXTERNAL ((2) << 21)
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#define AU1X00_MAC_CTRL_F (bit(20))
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#define AU1X00_MAC_CTRL_PM (bit(19))
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#define AU1X00_MAC_CTRL_PR (bit(18))
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#define AU1X00_MAC_CTRL_IF (bit(17))
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#define AU1X00_MAC_CTRL_PB (bit(16))
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#define AU1X00_MAC_CTRL_HO (bit(15))
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#define AU1X00_MAC_CTRL_HP (bit(13))
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#define AU1X00_MAC_CTRL_LC (bit(12))
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#define AU1X00_MAC_CTRL_DB (bit(11))
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#define AU1X00_MAC_CTRL_DR (bit(10))
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#define AU1X00_MAC_CTRL_AP (bit(8))
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#define AU1X00_MAC_CTRL_BL(x) ((x) << 6)
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#define AU1X00_MAC_CTRL_DC (bit(5))
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#define AU1X00_MAC_CTRL_TE (bit(3))
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#define AU1X00_MAC_CTRL_RE (bit(2))
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#define AU1X00_MAC_EN_JP (bit(6))
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#define AU1X00_MAC_EN_E2 (bit(5))
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#define AU1X00_MAC_EN_E1 (bit(4))
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#define AU1X00_MAC_EN_C (bit(3))
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#define AU1X00_MAC_EN_TS (bit(2))
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#define AU1X00_MAC_EN_E0 (bit(1))
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#define AU1X00_MAC_EN_CE (bit(0))
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#define AU1X00_MAC_ADDRHIGH_MASK (0xffff)_
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#define AU1X00_MAC_MIICTRL_PHYADDR(x) ((x & 0x1f) << 11)
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#define AU1X00_MAC_MIICTRL_MIIREG(x) ((x & 0x1f) << 6)
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#define AU1X00_MAC_MIICTRL_MW (bit(1))
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#define AU1X00_MAC_MIICTRL_MB (bit(0))
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#define AU1X00_MAC_MIIDATA_MASK (0xffff)
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#define AU1X00_MAC_FLOWCTRL_PT(x) (((x) & 0xffff) << 16)
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#define AU1X00_MAC_FLOWCTRL_PC (bit(2))
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#define AU1X00_MAC_FLOWCTRL_FE (bit(1))
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#define AU1X00_MAC_FLOWCTRL_FB (bit(0))
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#define AU1X00_MAC_DMA_RXSTAT_MI (bit(31))
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#define AU1X00_MAC_DMA_RXSTAT_PF (bit(30))
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#define AU1X00_MAC_DMA_RXSTAT_FF (bit(29))
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#define AU1X00_MAC_DMA_RXSTAT_BF (bit(28))
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#define AU1X00_MAC_DMA_RXSTAT_MF (bit(27))
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#define AU1X00_MAC_DMA_RXSTAT_UC (bit(26))
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#define AU1X00_MAC_DMA_RXSTAT_CF (bit(25))
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#define AU1X00_MAC_DMA_RXSTAT_LE (bit(24))
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#define AU1X00_MAC_DMA_RXSTAT_V2 (bit(23))
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#define AU1X00_MAC_DMA_RXSTAT_V1 (bit(22))
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#define AU1X00_MAC_DMA_RXSTAT_CR (bit(21))
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#define AU1X00_MAC_DMA_RXSTAT_DB (bit(20))
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#define AU1X00_MAC_DMA_RXSTAT_ME (bit(19))
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#define AU1X00_MAC_DMA_RXSTAT_FT (bit(18))
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#define AU1X00_MAC_DMA_RXSTAT_CS (bit(17))
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#define AU1X00_MAC_DMA_RXSTAT_FL (bit(16))
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#define AU1X00_MAC_DMA_RXSTAT_RF (bit(15))
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#define AU1X00_MAC_DMA_RXSTAT_WT (bit(14))
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#define AU1X00_MAC_DMA_RXSTAT_LEN(x) ((x) & 0x3fff)
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#define AU1X00_MAC_DMA_RXADDR_ADDR(x) ((x) & ~0x1f)
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#define AU1X00_MAC_DMA_RXADDR_CB_MASK (0x3 << 0x2)
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#define AU1X00_MAC_DMA_RXADDR_DN (bit(1))
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#define AU1X00_MAC_DMA_RXADDR_EN (bit(0))
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#define AU1X00_MAC_DMA_TXSTAT_PR (bit(31))
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#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10)
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#define AU1X00_MAC_DMA_TXSTAT_LO (bit(9))
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#define AU1X00_MAC_DMA_TXSTAT_DF (bit(8))
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#define AU1X00_MAC_DMA_TXSTAT_UR (bit(7))
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#define AU1X00_MAC_DMA_TXSTAT_EC (bit(6))
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#define AU1X00_MAC_DMA_TXSTAT_LC (bit(5))
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#define AU1X00_MAC_DMA_TXSTAT_ED (bit(4))
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#define AU1X00_MAC_DMA_TXSTAT_LS (bit(3))
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#define AU1X00_MAC_DMA_TXSTAT_NC (bit(2))
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#define AU1X00_MAC_DMA_TXSTAT_JT (bit(1))
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#define AU1X00_MAC_DMA_TXSTAT_FA (bit(0))
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#define AU1X00_MAC_DMA_TXADDR_ADDR(x) ((x) & ~0x1f)
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#define AU1X00_MAC_DMA_TXADDR_CB_MASK (0x3 << 0x2)
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#define AU1X00_MAC_DMA_TXADDR_DN (bit(1))
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#define AU1X00_MAC_DMA_TXADDR_EN (bit(0))
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typedef struct {
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volatile uint32_t rxdata;
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volatile uint32_t txdata;
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volatile uint32_t inten;
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volatile uint32_t intcause;
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volatile uint32_t fifoctrl;
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volatile uint32_t linectrl;
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volatile uint32_t mdmctrl;
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volatile uint32_t linestat;
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volatile uint32_t mdmstat;
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volatile uint32_t clkdiv;
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volatile uint32_t _resv[54];
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volatile uint32_t enable;
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} au1x00_uart_t;
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extern au1x00_uart_t *uart0;
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extern au1x00_uart_t *uart3;
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void static inline au_sync(void)
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{
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__asm__ volatile ("sync");
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}
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extern void mips_default_isr( int vector );
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/* Generate a software interrupt */
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extern int assert_sw_irq(uint32_t irqnum);
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/* Clear a software interrupt */
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extern int negate_sw_irq(uint32_t irqnum);
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#endif
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