forked from Imagelibrary/rtems
119 lines
4.0 KiB
C
119 lines
4.0 KiB
C
/**
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* @file
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* @ingroup RTEMSBSPsShared
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* @brief Xilinx Zynq Ultrascale+ MPSoC Peripheral memory map.
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*/
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2023 Reflex Aerospace GmbH
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*
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* Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP
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#define LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP
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/* Data derived from https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/PS-I/O-Peripherals-Registers */
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/* LPD IO Peripherals */
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#define ZYNQMP_UART0 (0xFF000000)
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#define ZYNQMP_UART1 (0xFF010000)
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#define ZYNQMP_I2C0 (0xFF020000)
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#define ZYNQMP_I2C1 (0xFF030000)
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#define ZYNQMP_SPI0 (0xFF040000)
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#define ZYNQMP_SPI1 (0xFF050000)
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#define ZYNQMP_CAN0 (0xFF060000)
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#define ZYNQMP_CAN1 (0xFF070000)
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#define ZYNQMP_GPIO (0xFF0A0000)
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#define ZYNQMP_GEM0 (0xFF0B0000)
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#define ZYNQMP_GEM1 (0xFF0C0000)
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#define ZYNQMP_GEM2 (0xFF0D0000)
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#define ZYNQMP_GEM3 (0xFF0E0000)
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#define ZYNQMP_QSPI (0xFF0F0000)
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#define ZYNQMP_NAND (0xFF100000)
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#define ZYNQMP_SD0 (0xFF160000)
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#define ZYNQMP_SD1 (0xFF170000)
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#define ZYNQMP_IPI_MSG (0xFF990000)
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#define ZYNQMP_USB0 (0xFF9D0000)
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#define ZYNQMP_USB1 (0xFF9E0000)
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#define ZYNQMP_AMS (0xFFA50000)
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#define ZYNQMP_PSSYSMON (0xFFA50800)
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#define ZYNQMP_PLSYSMON (0xFFA50C00)
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#define ZYNQMP_CSU_SWDT (0xFFCB0000)
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/* FPD IO Peripherals */
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#define ZYNQMP_SATA (0xFD0C0000)
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#define ZYNQMP_PCIE (0xFD0E0000)
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#define ZYNQMP_PCIE_IN (0xFD0E0800)
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#define ZYNQMP_PCIE_EG (0xFD0E0C00)
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#define ZYNQMP_PCIE_DMA (0xFD0F0000)
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#define ZYNQMP_SIOU (0xFD3D0000)
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#define ZYNQMP_GTR (0xFD400000)
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#define ZYNQMP_PCIE_ATTR (0xFD480000)
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#define ZYNQMP_DP (0xFD4A0000)
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#define ZYNQMP_GPU (0xFD4B0000)
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#define ZYNQMP_DP_DMA (0xFD4C0000)
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/* LPD System Registers */
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#define ZYNQMP_IPI (0xFF300000)
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#define ZYNQMP_TTC0 (0xFF110000)
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#define ZYNQMP_TTC1 (0xFF120000)
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#define ZYNQMP_TTC2 (0xFF130000)
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#define ZYNQMP_TTC3 (0xFF140000)
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#define ZYNQMP_LPD_SWDT (0xFF150000)
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#define ZYNQMP_XPPU (0xFF980000)
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#define ZYNQMP_XPPU_SINK (0xFF9C0000)
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#define ZYNQMP_PL_LPD (0xFF9B0000)
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#define ZYNQMP_OCM (0xFFA00000)
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#define ZYNQMP_LPD_FPD (0xFFA10000)
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#define ZYNQMP_RTC (0xFFA60000)
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#define ZYNQMP_OCM_XMPU (0xFFA70000)
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#define ZYNQMP_LPD_DMA (0xFFA80000)
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#define ZYNQMP_CSU_DMA (0xFFC80000)
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#define ZYNQMP_CSU (0xFFCA0000)
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#define ZYNQMP_BBRAM (0xFFCD0000)
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/* System Interrupt Table */
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/* SPIs */
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#define ZYNQMP_IRQ_UART_0 53
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#define ZYNQMP_IRQ_UART_1 54
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#define ZYNQMP_IRQ_TTC_0_0 68
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#define ZYNQMP_IRQ_TTC_0_1 69
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#define ZYNQMP_IRQ_TTC_0_2 70
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#define ZYNQMP_IRQ_TTC_1_0 71
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#define ZYNQMP_IRQ_TTC_1_1 72
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#define ZYNQMP_IRQ_TTC_1_2 73
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#define ZYNQMP_IRQ_TTC_2_0 74
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#define ZYNQMP_IRQ_TTC_2_1 75
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#define ZYNQMP_IRQ_TTC_2_2 76
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#define ZYNQMP_IRQ_TTC_3_0 77
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#define ZYNQMP_IRQ_TTC_3_1 78
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#define ZYNQMP_IRQ_TTC_3_2 79
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#endif /* LIBBSP_SHARED_PERIPHERAL_MAPS_ZYNQMP */
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