forked from Imagelibrary/rtems
298 lines
8.2 KiB
C
298 lines
8.2 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSDeviceGRLIBL4STAT
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*
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* @brief This header file defines the L4STAT register block interface.
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*/
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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/* Generated from spec:/dev/grlib/if/l4stat-header */
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#ifndef _GRLIB_L4STAT_REGS_H
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#define _GRLIB_L4STAT_REGS_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Generated from spec:/dev/grlib/if/l4stat */
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/**
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* @defgroup RTEMSDeviceGRLIBL4STAT L4STAT
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*
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* @ingroup RTEMSDeviceGRLIB
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*
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* @brief This group contains the L4STAT interfaces.
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*
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* @{
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*/
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/**
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* @defgroup RTEMSDeviceGRLIBL4STATCVAL Counter 0-15 value register (CVAL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define L4STAT_CVAL_CVAL_SHIFT 0
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#define L4STAT_CVAL_CVAL_MASK 0xffffffffU
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#define L4STAT_CVAL_CVAL_GET( _reg ) \
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( ( ( _reg ) & L4STAT_CVAL_CVAL_MASK ) >> \
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L4STAT_CVAL_CVAL_SHIFT )
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#define L4STAT_CVAL_CVAL_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_CVAL_CVAL_MASK ) | \
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( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
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L4STAT_CVAL_CVAL_MASK ) )
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#define L4STAT_CVAL_CVAL( _val ) \
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( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
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L4STAT_CVAL_CVAL_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBL4STATCCTRL Counter 0-15 control register (CCTRL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define L4STAT_CCTRL_NCPU_SHIFT 28
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#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U
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#define L4STAT_CCTRL_NCPU_GET( _reg ) \
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( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> \
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L4STAT_CCTRL_NCPU_SHIFT )
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#define L4STAT_CCTRL_NCPU_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_CCTRL_NCPU_MASK ) | \
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( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
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L4STAT_CCTRL_NCPU_MASK ) )
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#define L4STAT_CCTRL_NCPU( _val ) \
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( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
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L4STAT_CCTRL_NCPU_MASK )
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#define L4STAT_CCTRL_NCNT_SHIFT 23
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#define L4STAT_CCTRL_NCNT_MASK 0xf800000U
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#define L4STAT_CCTRL_NCNT_GET( _reg ) \
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( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> \
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L4STAT_CCTRL_NCNT_SHIFT )
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#define L4STAT_CCTRL_NCNT_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_CCTRL_NCNT_MASK ) | \
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( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
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L4STAT_CCTRL_NCNT_MASK ) )
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#define L4STAT_CCTRL_NCNT( _val ) \
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( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
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L4STAT_CCTRL_NCNT_MASK )
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#define L4STAT_CCTRL_MC 0x400000U
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#define L4STAT_CCTRL_IA 0x200000U
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#define L4STAT_CCTRL_DS 0x100000U
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#define L4STAT_CCTRL_EE 0x80000U
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#define L4STAT_CCTRL_AE 0x40000U
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#define L4STAT_CCTRL_EL 0x20000U
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#define L4STAT_CCTRL_CD 0x10000U
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#define L4STAT_CCTRL_SU_SHIFT 14
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#define L4STAT_CCTRL_SU_MASK 0xc000U
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#define L4STAT_CCTRL_SU_GET( _reg ) \
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( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> \
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L4STAT_CCTRL_SU_SHIFT )
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#define L4STAT_CCTRL_SU_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_CCTRL_SU_MASK ) | \
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( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
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L4STAT_CCTRL_SU_MASK ) )
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#define L4STAT_CCTRL_SU( _val ) \
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( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
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L4STAT_CCTRL_SU_MASK )
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#define L4STAT_CCTRL_CL 0x2000U
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#define L4STAT_CCTRL_EN 0x1000U
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#define L4STAT_CCTRL_EVENT_ID_SHIFT 4
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#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U
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#define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \
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( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> \
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L4STAT_CCTRL_EVENT_ID_SHIFT )
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#define L4STAT_CCTRL_EVENT_ID_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \
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( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
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L4STAT_CCTRL_EVENT_ID_MASK ) )
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#define L4STAT_CCTRL_EVENT_ID( _val ) \
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( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
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L4STAT_CCTRL_EVENT_ID_MASK )
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#define L4STAT_CCTRL_CPU_AHBM_SHIFT 0
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#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU
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#define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \
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( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> \
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L4STAT_CCTRL_CPU_AHBM_SHIFT )
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#define L4STAT_CCTRL_CPU_AHBM_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \
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( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
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L4STAT_CCTRL_CPU_AHBM_MASK ) )
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#define L4STAT_CCTRL_CPU_AHBM( _val ) \
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( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
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L4STAT_CCTRL_CPU_AHBM_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBL4STATCSVAL \
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* Counter 0-15 max/latch register (CSVAL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define L4STAT_CSVAL_CSVAL_SHIFT 0
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#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU
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#define L4STAT_CSVAL_CSVAL_GET( _reg ) \
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( ( ( _reg ) & L4STAT_CSVAL_CSVAL_MASK ) >> \
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L4STAT_CSVAL_CSVAL_SHIFT )
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#define L4STAT_CSVAL_CSVAL_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_CSVAL_CSVAL_MASK ) | \
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( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
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L4STAT_CSVAL_CSVAL_MASK ) )
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#define L4STAT_CSVAL_CSVAL( _val ) \
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( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
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L4STAT_CSVAL_CSVAL_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRLIBL4STATTSTAMP Timestamp register (TSTAMP)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define L4STAT_TSTAMP_TSTAMP_SHIFT 0
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#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU
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#define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \
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( ( ( _reg ) & L4STAT_TSTAMP_TSTAMP_MASK ) >> \
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L4STAT_TSTAMP_TSTAMP_SHIFT )
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#define L4STAT_TSTAMP_TSTAMP_SET( _reg, _val ) \
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( ( ( _reg ) & ~L4STAT_TSTAMP_TSTAMP_MASK ) | \
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( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
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L4STAT_TSTAMP_TSTAMP_MASK ) )
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#define L4STAT_TSTAMP_TSTAMP( _val ) \
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( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
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L4STAT_TSTAMP_TSTAMP_MASK )
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/** @} */
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/**
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* @brief This structure defines the L4STAT register block memory map.
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*/
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typedef struct l4stat {
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/**
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* @brief See @ref RTEMSDeviceGRLIBL4STATCVAL.
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*/
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uint32_t cval_0;
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uint32_t reserved_4_3c[ 14 ];
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/**
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* @brief See @ref RTEMSDeviceGRLIBL4STATCVAL.
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*/
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uint32_t cval_1;
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uint32_t reserved_40_80[ 16 ];
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/**
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* @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL.
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*/
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uint32_t cctrl_0;
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uint32_t reserved_84_cc[ 18 ];
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/**
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* @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL.
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*/
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uint32_t cctrl_1;
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uint32_t reserved_d0_100[ 12 ];
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/**
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* @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL.
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*/
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uint32_t csval_0;
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uint32_t reserved_104_13c[ 14 ];
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/**
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* @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL.
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*/
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uint32_t csval_1;
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uint32_t reserved_140_180[ 16 ];
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/**
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* @brief See @ref RTEMSDeviceGRLIBL4STATTSTAMP.
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*/
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uint32_t tstamp;
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} l4stat;
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _GRLIB_L4STAT_REGS_H */
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