forked from Imagelibrary/rtems
631 lines
17 KiB
C
631 lines
17 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSDeviceGRGPIO
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*
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* @brief This header file defines the GRGPIO register block interface.
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*/
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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/* Generated from spec:/dev/grlib/if/grgpio-header */
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#ifndef _GRLIB_GRGPIO_REGS_H
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#define _GRLIB_GRGPIO_REGS_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Generated from spec:/dev/grlib/if/grgpio */
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/**
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* @defgroup RTEMSDeviceGRGPIO GRGPIO
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*
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* @ingroup RTEMSDeviceGRLIB
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*
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* @brief This group contains the GRGPIO interfaces.
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*
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* @{
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*/
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/**
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* @defgroup RTEMSDeviceGRGPIODATA I/O port data register (DATA)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_DATA_DATA_SHIFT 0
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#define GRGPIO_DATA_DATA_MASK 0xffffffffU
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#define GRGPIO_DATA_DATA_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_DATA_DATA_MASK ) >> \
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GRGPIO_DATA_DATA_SHIFT )
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#define GRGPIO_DATA_DATA_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_DATA_DATA_MASK ) | \
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( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
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GRGPIO_DATA_DATA_MASK ) )
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#define GRGPIO_DATA_DATA( _val ) \
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( ( ( _val ) << GRGPIO_DATA_DATA_SHIFT ) & \
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GRGPIO_DATA_DATA_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOOUTPUT I/O port output register (OUTPUT)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_OUTPUT_DATA_SHIFT 0
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#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU
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#define GRGPIO_OUTPUT_DATA_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_OUTPUT_DATA_MASK ) >> \
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GRGPIO_OUTPUT_DATA_SHIFT )
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#define GRGPIO_OUTPUT_DATA_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_OUTPUT_DATA_MASK ) | \
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( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
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GRGPIO_OUTPUT_DATA_MASK ) )
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#define GRGPIO_OUTPUT_DATA( _val ) \
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( ( ( _val ) << GRGPIO_OUTPUT_DATA_SHIFT ) & \
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GRGPIO_OUTPUT_DATA_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIODIRECTION I/O port direction register (DIRECTION)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_DIRECTION_DIR_SHIFT 0
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#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU
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#define GRGPIO_DIRECTION_DIR_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_DIRECTION_DIR_MASK ) >> \
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GRGPIO_DIRECTION_DIR_SHIFT )
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#define GRGPIO_DIRECTION_DIR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_DIRECTION_DIR_MASK ) | \
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( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
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GRGPIO_DIRECTION_DIR_MASK ) )
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#define GRGPIO_DIRECTION_DIR( _val ) \
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( ( ( _val ) << GRGPIO_DIRECTION_DIR_SHIFT ) & \
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GRGPIO_DIRECTION_DIR_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOIMASK Interrupt mask register (IMASK)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_IMASK_MASK_SHIFT 0
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#define GRGPIO_IMASK_MASK_MASK 0xffffffffU
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#define GRGPIO_IMASK_MASK_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IMASK_MASK_MASK ) >> \
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GRGPIO_IMASK_MASK_SHIFT )
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#define GRGPIO_IMASK_MASK_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IMASK_MASK_MASK ) | \
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( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
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GRGPIO_IMASK_MASK_MASK ) )
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#define GRGPIO_IMASK_MASK( _val ) \
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( ( ( _val ) << GRGPIO_IMASK_MASK_SHIFT ) & \
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GRGPIO_IMASK_MASK_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOIPOL Interrupt polarity register (IPOL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_IPOL_POL_SHIFT 0
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#define GRGPIO_IPOL_POL_MASK 0xffffffffU
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#define GRGPIO_IPOL_POL_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IPOL_POL_MASK ) >> \
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GRGPIO_IPOL_POL_SHIFT )
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#define GRGPIO_IPOL_POL_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IPOL_POL_MASK ) | \
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( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
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GRGPIO_IPOL_POL_MASK ) )
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#define GRGPIO_IPOL_POL( _val ) \
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( ( ( _val ) << GRGPIO_IPOL_POL_SHIFT ) & \
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GRGPIO_IPOL_POL_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOIEDGE Interrupt edge register (IEDGE)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_IEDGE_EDGE_SHIFT 0
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#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU
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#define GRGPIO_IEDGE_EDGE_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IEDGE_EDGE_MASK ) >> \
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GRGPIO_IEDGE_EDGE_SHIFT )
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#define GRGPIO_IEDGE_EDGE_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IEDGE_EDGE_MASK ) | \
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( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
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GRGPIO_IEDGE_EDGE_MASK ) )
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#define GRGPIO_IEDGE_EDGE( _val ) \
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( ( ( _val ) << GRGPIO_IEDGE_EDGE_SHIFT ) & \
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GRGPIO_IEDGE_EDGE_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOBYPASS Bypass register (BYPASS)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_BYPASS_BYPASS_SHIFT 0
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#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU
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#define GRGPIO_BYPASS_BYPASS_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_BYPASS_BYPASS_MASK ) >> \
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GRGPIO_BYPASS_BYPASS_SHIFT )
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#define GRGPIO_BYPASS_BYPASS_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_BYPASS_BYPASS_MASK ) | \
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( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
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GRGPIO_BYPASS_BYPASS_MASK ) )
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#define GRGPIO_BYPASS_BYPASS( _val ) \
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( ( ( _val ) << GRGPIO_BYPASS_BYPASS_SHIFT ) & \
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GRGPIO_BYPASS_BYPASS_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOCAP Capability register (CAP)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_CAP_PU 0x40000U
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#define GRGPIO_CAP_IER 0x20000U
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#define GRGPIO_CAP_IFL 0x10000U
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#define GRGPIO_CAP_IRQGEN_SHIFT 8
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#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U
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#define GRGPIO_CAP_IRQGEN_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_CAP_IRQGEN_MASK ) >> \
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GRGPIO_CAP_IRQGEN_SHIFT )
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#define GRGPIO_CAP_IRQGEN_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_CAP_IRQGEN_MASK ) | \
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( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
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GRGPIO_CAP_IRQGEN_MASK ) )
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#define GRGPIO_CAP_IRQGEN( _val ) \
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( ( ( _val ) << GRGPIO_CAP_IRQGEN_SHIFT ) & \
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GRGPIO_CAP_IRQGEN_MASK )
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#define GRGPIO_CAP_NLINES_SHIFT 0
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#define GRGPIO_CAP_NLINES_MASK 0x1fU
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#define GRGPIO_CAP_NLINES_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_CAP_NLINES_MASK ) >> \
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GRGPIO_CAP_NLINES_SHIFT )
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#define GRGPIO_CAP_NLINES_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_CAP_NLINES_MASK ) | \
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( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
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GRGPIO_CAP_NLINES_MASK ) )
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#define GRGPIO_CAP_NLINES( _val ) \
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( ( ( _val ) << GRGPIO_CAP_NLINES_SHIFT ) & \
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GRGPIO_CAP_NLINES_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOIRQMAPR \
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* Interrupt map register n, where n = 0 .. 3 (IRQMAPR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24
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#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f000000U
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#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) >> \
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GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT )
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#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) )
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#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_0_MASK )
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#define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16
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#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U
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#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) >> \
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GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT )
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#define GRGPIO_IRQMAPR_IRQMAP_I_1_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) | \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_1_MASK ) )
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#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_1_MASK )
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#define GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8
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#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U
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#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) >> \
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GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT )
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#define GRGPIO_IRQMAPR_IRQMAP_I_2_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) | \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_2_MASK ) )
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#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_2_MASK )
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#define GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0
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#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU
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#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) >> \
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GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT )
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#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) )
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#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \
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( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
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GRGPIO_IRQMAPR_IRQMAP_I_3_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOIAVAIL Interrupt available register (IAVAIL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_IAVAIL_IMASK_SHIFT 0
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#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU
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#define GRGPIO_IAVAIL_IMASK_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IAVAIL_IMASK_MASK ) >> \
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GRGPIO_IAVAIL_IMASK_SHIFT )
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#define GRGPIO_IAVAIL_IMASK_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IAVAIL_IMASK_MASK ) | \
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( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
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GRGPIO_IAVAIL_IMASK_MASK ) )
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#define GRGPIO_IAVAIL_IMASK( _val ) \
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( ( ( _val ) << GRGPIO_IAVAIL_IMASK_SHIFT ) & \
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GRGPIO_IAVAIL_IMASK_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOIFLAG Interrupt flag register (IFLAG)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_IFLAG_IFLAG_SHIFT 0
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#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU
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#define GRGPIO_IFLAG_IFLAG_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IFLAG_IFLAG_MASK ) >> \
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GRGPIO_IFLAG_IFLAG_SHIFT )
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#define GRGPIO_IFLAG_IFLAG_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IFLAG_IFLAG_MASK ) | \
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( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
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GRGPIO_IFLAG_IFLAG_MASK ) )
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#define GRGPIO_IFLAG_IFLAG( _val ) \
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( ( ( _val ) << GRGPIO_IFLAG_IFLAG_SHIFT ) & \
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GRGPIO_IFLAG_IFLAG_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOIPEN Interrupt enable register (IPEN)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_IPEN_IPEN_SHIFT 0
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#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU
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#define GRGPIO_IPEN_IPEN_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_IPEN_IPEN_MASK ) >> \
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GRGPIO_IPEN_IPEN_SHIFT )
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#define GRGPIO_IPEN_IPEN_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_IPEN_IPEN_MASK ) | \
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( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
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GRGPIO_IPEN_IPEN_MASK ) )
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#define GRGPIO_IPEN_IPEN( _val ) \
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( ( ( _val ) << GRGPIO_IPEN_IPEN_SHIFT ) & \
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GRGPIO_IPEN_IPEN_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOPULSE Pulse register (PULSE)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRGPIO_PULSE_PULSE_SHIFT 0
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#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU
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#define GRGPIO_PULSE_PULSE_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_PULSE_PULSE_MASK ) >> \
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GRGPIO_PULSE_PULSE_SHIFT )
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#define GRGPIO_PULSE_PULSE_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_PULSE_PULSE_MASK ) | \
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( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
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GRGPIO_PULSE_PULSE_MASK ) )
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#define GRGPIO_PULSE_PULSE( _val ) \
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( ( ( _val ) << GRGPIO_PULSE_PULSE_SHIFT ) & \
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GRGPIO_PULSE_PULSE_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRGPIOLOR Logical-OR registers (LOR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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|
*/
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|
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#define GRGPIO_LOR_DATA_SHIFT 0
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#define GRGPIO_LOR_DATA_MASK 0xffffffffU
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#define GRGPIO_LOR_DATA_GET( _reg ) \
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( ( ( _reg ) & GRGPIO_LOR_DATA_MASK ) >> \
|
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GRGPIO_LOR_DATA_SHIFT )
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|
#define GRGPIO_LOR_DATA_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRGPIO_LOR_DATA_MASK ) | \
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( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
|
|
GRGPIO_LOR_DATA_MASK ) )
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|
#define GRGPIO_LOR_DATA( _val ) \
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( ( ( _val ) << GRGPIO_LOR_DATA_SHIFT ) & \
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GRGPIO_LOR_DATA_MASK )
|
|
|
|
/** @} */
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|
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|
/**
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* @defgroup RTEMSDeviceGRGPIOLAND Logical-AND registers (LAND)
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*
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|
* @brief This group contains register bit definitions.
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|
*
|
|
* @{
|
|
*/
|
|
|
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#define GRGPIO_LAND_DATA_SHIFT 0
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#define GRGPIO_LAND_DATA_MASK 0xffffffffU
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|
#define GRGPIO_LAND_DATA_GET( _reg ) \
|
|
( ( ( _reg ) & GRGPIO_LAND_DATA_MASK ) >> \
|
|
GRGPIO_LAND_DATA_SHIFT )
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|
#define GRGPIO_LAND_DATA_SET( _reg, _val ) \
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|
( ( ( _reg ) & ~GRGPIO_LAND_DATA_MASK ) | \
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|
( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
|
|
GRGPIO_LAND_DATA_MASK ) )
|
|
#define GRGPIO_LAND_DATA( _val ) \
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|
( ( ( _val ) << GRGPIO_LAND_DATA_SHIFT ) & \
|
|
GRGPIO_LAND_DATA_MASK )
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* @defgroup RTEMSDeviceGRGPIOLXOR Logical-XOR registers (LXOR)
|
|
*
|
|
* @brief This group contains register bit definitions.
|
|
*
|
|
* @{
|
|
*/
|
|
|
|
#define GRGPIO_LXOR_DATA_SHIFT 0
|
|
#define GRGPIO_LXOR_DATA_MASK 0xffffffffU
|
|
#define GRGPIO_LXOR_DATA_GET( _reg ) \
|
|
( ( ( _reg ) & GRGPIO_LXOR_DATA_MASK ) >> \
|
|
GRGPIO_LXOR_DATA_SHIFT )
|
|
#define GRGPIO_LXOR_DATA_SET( _reg, _val ) \
|
|
( ( ( _reg ) & ~GRGPIO_LXOR_DATA_MASK ) | \
|
|
( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
|
|
GRGPIO_LXOR_DATA_MASK ) )
|
|
#define GRGPIO_LXOR_DATA( _val ) \
|
|
( ( ( _val ) << GRGPIO_LXOR_DATA_SHIFT ) & \
|
|
GRGPIO_LXOR_DATA_MASK )
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* @brief This structure defines the GRGPIO register block memory map.
|
|
*/
|
|
typedef struct grgpio {
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIODATA.
|
|
*/
|
|
uint32_t data;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOOUTPUT.
|
|
*/
|
|
uint32_t output;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIODIRECTION.
|
|
*/
|
|
uint32_t direction;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOIMASK.
|
|
*/
|
|
uint32_t imask;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOIPOL.
|
|
*/
|
|
uint32_t ipol;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOIEDGE.
|
|
*/
|
|
uint32_t iedge;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOBYPASS.
|
|
*/
|
|
uint32_t bypass;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOCAP.
|
|
*/
|
|
uint32_t cap;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOIRQMAPR.
|
|
*/
|
|
uint32_t irqmapr[ 8 ];
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOIAVAIL.
|
|
*/
|
|
uint32_t iavail;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOIFLAG.
|
|
*/
|
|
uint32_t iflag;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOIPEN.
|
|
*/
|
|
uint32_t ipen;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOPULSE.
|
|
*/
|
|
uint32_t pulse;
|
|
|
|
uint32_t reserved_50_54;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLOR.
|
|
*/
|
|
uint32_t lor_output;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLOR.
|
|
*/
|
|
uint32_t lor_direction;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLOR.
|
|
*/
|
|
uint32_t lor_imask;
|
|
|
|
uint32_t reserved_60_64;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLAND.
|
|
*/
|
|
uint32_t land_output;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLAND.
|
|
*/
|
|
uint32_t land_direction;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLAND.
|
|
*/
|
|
uint32_t land_imask;
|
|
|
|
uint32_t reserved_70_74;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLXOR.
|
|
*/
|
|
uint32_t lxor_output;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLXOR.
|
|
*/
|
|
uint32_t lxor_direction;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRGPIOLXOR.
|
|
*/
|
|
uint32_t lxor_imask;
|
|
} grgpio;
|
|
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _GRLIB_GRGPIO_REGS_H */
|