forked from Imagelibrary/rtems
fd2f9d40b5
This adds Xilinx's driver for the Xilinx GQSPI controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/spi/VERSION.
103 lines
3.7 KiB
C
103 lines
3.7 KiB
C
/******************************************************************************
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* Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xqspipsu_control.h
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* @addtogroup Overview
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* @{
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*
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* This is the header file for the implementation of QSPIPSU driver.
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* Generic QSPI interface allows for communication to any QSPI slave device.
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* GQSPI contains a GENFIFO into which the bus transfers required are to be
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* pushed with appropriate configuration. The controller provides TX and RX
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* FIFO's and a DMA to be used for RX transfers. The controller executes each
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* GENFIFO entry noting the configuration and places data on the bus as required
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*
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- -----------------------------------------------.
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* 1.11 akm 03/09/20 First release
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* 1.13 akm 01/04/21 Fix MISRA-C violations.
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* 1.15 akm 03/03/22 Enable tapdelay settings for applications on
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* Microblaze platform.
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*
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* </pre>
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*
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******************************************************************************/
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/** @cond INTERNAL */
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#ifndef XQSPIPSU_CONTROL_H_ /**< prevent circular inclusions */
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#define XQSPIPSU_CONTROL_H_ /**< by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xqspipsu.h"
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
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#define TAPDLY_BYPASS_VALVE_40MHZ 0x01U
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#define TAPDLY_BYPASS_VALVE_100MHZ 0x01U
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#define USE_DLY_LPBK 0x01U
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#define USE_DATA_DLY_ADJ 0x01U
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#define DATA_DLY_ADJ_DLY 0X02U
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#define LPBK_DLY_ADJ_DLY0 0X02U
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#define LPBK_DLY_ADJ_DLY1 0X02U
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#endif
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#ifdef __MICROBLAZE__
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#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
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#endif
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/************************** Function Prototypes ******************************/
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void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
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u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
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void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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u32 StatusReg);
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void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg);
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void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
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void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr,
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XQspiPsu_Msg *Msg);
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void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr,
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XQspiPsu_Msg *Msg);
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void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
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void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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u32 *GenFifoEntry);
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void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
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u32 *GenFifoEntry);
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u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr,
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const XQspiPsu_Msg *FlashMsg);
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void XQspiPsu_PollDataHandler(XQspiPsu *InstancePtr, u32 StatusReg);
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u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
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void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr);
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void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size);
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void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Size);
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#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
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s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,
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u32 LPBKDelay, u32 Datadelay);
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s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* XQSPIPSU_CONTROL_H_ */
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/** @endcond */
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/** @} */
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