forked from Imagelibrary/rtems
1bba349478
This removes the headers imported from the embeddedsw repository in favor of a much thinner shim. This also removes the complicated build system configuration necessary to support use of these headers. The primary reason for removal is that certain external Xilinx libraries also require use of these headers and this causes version mismatches and header conflicts that can be avoided.
488 lines
17 KiB
C
488 lines
17 KiB
C
/******************************************************************************
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* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xnandpsu_hw.h
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* @addtogroup Overview
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* @{
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*
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* This file contains identifiers and low-level macros/functions for the Arasan
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* NAND flash controller driver.
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*
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* See xnandpsu.h for more information.
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*
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* @note None
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- ---------- -----------------------------------------------
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* 1.0 nm 05/06/2014 First Release
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* 2.0 sb 11/04/2014 Changed XNANDPSU_ECC_SLC_MLC_MASK to
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* XNANDPSU_ECC_HAMMING_BCH_MASK.
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* 1.7 akm 09/03/20 Updated the Makefile to support parallel make
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* execution.
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* </pre>
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*
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******************************************************************************/
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#ifndef XNANDPSU_HW_H /* prevent circular inclusions */
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#define XNANDPSU_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#ifndef __rtems__
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#include "xil_io.h"
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#else
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#include <bsp/xil-compat.h>
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#endif
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/************************** Constant Definitions *****************************/
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/************************** Register Offset Definitions **********************/
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#define XNANDPSU_PKT_OFFSET 0x00U /**< Packet Register */
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#define XNANDPSU_MEM_ADDR1_OFFSET 0x04U /**< Memory Address
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Register 1 */
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#define XNANDPSU_MEM_ADDR2_OFFSET 0x08U /**< Memory Address
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Register 2 */
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#define XNANDPSU_CMD_OFFSET 0x0CU /**< Command Register */
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#define XNANDPSU_PROG_OFFSET 0x10U /**< Program Register */
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#define XNANDPSU_INTR_STS_EN_OFFSET 0x14U /**< Interrupt Status
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Enable Register */
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#define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U /**< Interrupt Signal
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Enable Register */
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#define XNANDPSU_INTR_STS_OFFSET 0x1CU /**< Interrupt Status
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Register */
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#define XNANDPSU_READY_BUSY_OFFSET 0x20U /**< Ready/Busy status
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Register */
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#define XNANDPSU_FLASH_STS_OFFSET 0x28U /**< Flash Status Register */
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#define XNANDPSU_TIMING_OFFSET 0x2CU /**< Timing Register */
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#define XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U /**< Buffer Data Port
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Register */
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#define XNANDPSU_ECC_OFFSET 0x34U /**< ECC Register */
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#define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U /**< ECC Error Count
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Register */
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#define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU /**< ECC Spare Command
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Register */
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#define XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U /**< Error Count 1bit
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Register */
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#define XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U /**< Error Count 2bit
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Register */
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#define XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U /**< Error Count 3bit
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Register */
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#define XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU /**< Error Count 4bit
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Register */
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#define XNANDPSU_CPU_REL_OFFSET 0x58U /**< CPU Release Register */
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#define XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU /**< Error Count 5bit
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Register */
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#define XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U /**< Error Count 6bit
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Register */
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#define XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U /**< Error Count 7bit
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Register */
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#define XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U /**< Error Count 8bit
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Register */
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#define XNANDPSU_DATA_INTF_OFFSET 0x6CU /**< Data Interface Register */
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#define XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U /**< DMA System Address 0
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Register */
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#define XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U /**< DMA System Address 1
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Register */
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#define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U /**< DMA Buffer Boundary
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Register */
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#define XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U /**< Slave DMA Configuration
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Register */
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/** @name Packet Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU /**< Packet Size */
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#define XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U /**< Packet Count*/
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#define XNANDPSU_PKT_PKT_CNT_SHIFT 12U /**< Packet Count Shift */
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/* @} */
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/** @name Memory Address Register 1 bit definitions and masks
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* @{
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*/
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#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU /**< Column Address
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Mask */
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#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U /**< Page, Block
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Address Mask */
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#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U /**< Page Shift */
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/* @} */
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/** @name Memory Address Register 2 bit definitions and masks
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* @{
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*/
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#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU /**< Memory Address
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*/
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#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U /**< Bus Width */
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#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U /**< BCH Mode
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Value */
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#define XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U /**< Flash
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Connection Mode */
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#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U /**< Chip Select */
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#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U /**< Chip select
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shift */
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#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U /**< Bus width shift */
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#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U
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/* @} */
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/** @name Command Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_CMD_CMD1_MASK 0x000000FFU /**< 1st Cycle
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Command */
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#define XNANDPSU_CMD_CMD2_MASK 0x0000FF00U /**< 2nd Cycle
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Command */
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#define XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U /**< Page Size */
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#define XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U /**< DMA Enable
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Mode */
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#define XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U /**< Number of
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Address Cycles */
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#define XNANDPSU_CMD_ECC_ON_MASK 0x80000000U /**< ECC ON/OFF */
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#define XNANDPSU_CMD_CMD2_SHIFT 8U /**< 2nd Cycle Command
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Shift */
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#define XNANDPSU_CMD_PG_SIZE_SHIFT 23U /**< Page Size Shift */
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#define XNANDPSU_CMD_DMA_EN_SHIFT 26U /**< DMA Enable Shift */
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#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U /**< Number of Address
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Cycles Shift */
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#define XNANDPSU_CMD_ECC_ON_SHIFT 31U /**< ECC ON/OFF */
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/* @} */
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/** @name Program Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_PROG_RD_MASK 0x00000001U /**< Read */
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#define XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U /**< Multi Die */
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#define XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U /**< Block Erase */
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#define XNANDPSU_PROG_RD_STS_MASK 0x00000008U /**< Read Status */
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#define XNANDPSU_PROG_PG_PROG_MASK 0x00000010U /**< Page Program */
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#define XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U /**< Multi Die Rd */
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#define XNANDPSU_PROG_RD_ID_MASK 0x00000040U /**< Read ID */
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#define XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U /**< Read Param
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Page */
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#define XNANDPSU_PROG_RST_MASK 0x00000100U /**< Reset */
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#define XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U /**< Get Features */
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#define XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U /**< Set Features */
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#define XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U /**< Read Unique
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ID */
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#define XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U /**< Read Status
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Enhanced */
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#define XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U /**< Read
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Interleaved */
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#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U /**< Change Read
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Column
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Enhanced */
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#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U /**< Copy Back
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Interleaved */
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#define XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U /**< Read Cache
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Start */
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#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U /**< Read Cache
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Sequential */
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#define XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U /**< Read Cache
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Random */
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#define XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U /**< Read Cache
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End */
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#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U /**< Small Data
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Move */
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#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U /**< Change Row
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Address */
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#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U /**< Change Row
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Address End */
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#define XNANDPSU_PROG_RST_LUN_MASK 0x00800000U /**< Reset LUN */
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#define XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U /**< Enhanced
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Program Page
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Register Clear */
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#define XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U /**< Volume Select */
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#define XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U /**< ODT Configure */
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/* @} */
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/** @name Interrupt Status Enable Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
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Write Ready
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Status
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Enable */
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#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
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Read Ready
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Status
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Enable */
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#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
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Complete
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Status
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Enable */
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#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
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Bit Error
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Status
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Enable */
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#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
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Bit Error
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Status
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Enable,
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BCH Detect
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Error
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Status
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Enable */
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#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
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Status
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Enable */
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#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
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AHB Status
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Enable */
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/* @} */
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/** @name Interrupt Signal Enable Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
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Write Ready
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Signal
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Enable */
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#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
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Read Ready
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Signal
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Enable */
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#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
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Complete
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Signal
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Enable */
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#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
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Bit Error
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Signal
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Enable */
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#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
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Bit Error
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Signal
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Enable,
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BCH Detect
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Error
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Signal
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Enable */
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#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
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Signal
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Enable */
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#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
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AHB Signal
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Enable */
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/* @} */
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/** @name Interrupt Status Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
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Write
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Ready */
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#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
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Read
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Ready */
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#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
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Complete */
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#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
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Bit Error */
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#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
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Bit Error,
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BCH Detect
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Error */
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#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
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Interrupt
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*/
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#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
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AHB */
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/* @} */
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/** @name Interrupt bit definitions and masks
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* @{
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*/
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#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer Write
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Ready Status
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Enable */
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#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer Read
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Ready Status
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Enable */
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#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
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Complete Status
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Enable */
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#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi Bit Error
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Status Enable */
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#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single Bit Error
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Status Enable,
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BCH Detect Error
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Status Enable */
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#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA Status
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Enable */
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#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error AHB Status
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Enable */
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/* @} */
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/** @name ID2 Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU /**< MSB Device ID */
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/* @} */
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/** @name Flash Status Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU /**< Flash Status
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Value */
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/* @} */
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/** @name Timing Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U /**< Change column
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setup time */
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#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U /**< Slow/Fast device
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*/
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#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U /**< Write/Read data
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transaction value
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*/
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#define XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U /**< Address latch
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enable to Data
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loading time */
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/* @} */
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/** @name ECC Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU /**< ECC address */
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#define XNANDPSU_ECC_SIZE_MASK 0x01FF0000U /**< ECC size */
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#define XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U /**< Hamming/BCH
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support */
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/* @} */
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/** @name ECC Error Count Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU /**< Packet
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bound error
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count */
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#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U /**< Page
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bound error
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count */
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/* @} */
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/** @name ECC Spare Command Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU /**< ECC
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spare
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command */
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#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U /**< Number
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of ECC/
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spare
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address
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cycles */
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/* @} */
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/** @name Data Interface Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U /**< SDR mode */
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#define XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U /**< NVDDR mode */
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#define XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U /**< NVDDR2 mode */
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#define XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U /**< Data
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Interface */
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#define XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U /**< NVDDR mode shift */
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#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U /**< Data Interface Shift */
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/* @} */
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/** @name DMA Buffer Boundary Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U /**< DMA buffer
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boundary */
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#define XNANDPSU_DMA_BUF_BND_4K 0x0U
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#define XNANDPSU_DMA_BUF_BND_8K 0x1U
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#define XNANDPSU_DMA_BUF_BND_16K 0x2U
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#define XNANDPSU_DMA_BUF_BND_32K 0x3U
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#define XNANDPSU_DMA_BUF_BND_64K 0x4U
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#define XNANDPSU_DMA_BUF_BND_128K 0x5U
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#define XNANDPSU_DMA_BUF_BND_256K 0x6U
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#define XNANDPSU_DMA_BUF_BND_512K 0x7U
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/* @} */
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/** @name Slave DMA Configuration Register bit definitions and masks
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* @{
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*/
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#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U /**< Slave
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DMA
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Transfer
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Direction
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*/
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#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU /**< Slave
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DMA
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Transfer
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Count */
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#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U /**< Slave
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DMA
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Burst
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Size */
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#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U /**< DMA
|
|
Timeout
|
|
Counter
|
|
Value */
|
|
#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U /**< Slave
|
|
DMA
|
|
Enable */
|
|
/* @} */
|
|
|
|
/**************************** Type Definitions *******************************/
|
|
|
|
/***************** Macros (Inline Functions) Definitions *********************/
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* This macro reads the given register.
|
|
*
|
|
* @param BaseAddress is the base address of controller registers.
|
|
* @param RegOffset is the register offset to be read.
|
|
*
|
|
* @return The 32-bit value of the register.
|
|
*
|
|
* @note C-style signature:
|
|
* u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
|
|
*
|
|
*****************************************************************************/
|
|
#define XNandPsu_ReadReg(BaseAddress, RegOffset) \
|
|
Xil_In32((BaseAddress) + (RegOffset))
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* This macro writes the given register.
|
|
*
|
|
* @param BaseAddress is the the base address of controller registers.
|
|
* @param RegOffset is the register offset to be written.
|
|
* @param Data is the the 32-bit value to write to the register.
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note C-style signature:
|
|
* void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
|
|
*
|
|
******************************************************************************/
|
|
#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data) \
|
|
Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
|
|
/************************** Variable Definitions *****************************/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* XNANDPSU_HW_H end of protection macro */
|
|
/** @} */
|