forked from Imagelibrary/rtems
99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup DevIRQGIC
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*
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* @brief This header file provides interfaces of the ARM Generic Interrupt
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* Controller (GIC) support.
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*/
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/*
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* Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
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#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
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#include <bsp.h>
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#include <dev/irq/arm-gic.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/**
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* @addtogroup DevIRQGIC
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*
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* @{
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*/
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#define ARM_GIC_IRQ_SGI_0 0
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#define ARM_GIC_IRQ_SGI_1 1
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#define ARM_GIC_IRQ_SGI_2 2
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#define ARM_GIC_IRQ_SGI_3 3
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#define ARM_GIC_IRQ_SGI_5 5
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#define ARM_GIC_IRQ_SGI_6 6
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#define ARM_GIC_IRQ_SGI_7 7
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#define ARM_GIC_IRQ_SGI_8 8
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#define ARM_GIC_IRQ_SGI_9 9
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#define ARM_GIC_IRQ_SGI_10 10
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#define ARM_GIC_IRQ_SGI_11 11
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#define ARM_GIC_IRQ_SGI_12 12
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#define ARM_GIC_IRQ_SGI_13 13
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#define ARM_GIC_IRQ_SGI_14 14
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#define ARM_GIC_IRQ_SGI_15 15
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#define ARM_GIC_IRQ_SGI_LAST 15
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#define ARM_GIC_IRQ_PPI_LAST 31
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#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
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rtems_status_code arm_gic_irq_set_group(
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rtems_vector_number vector,
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gic_group group
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);
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rtems_status_code arm_gic_irq_get_group(
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rtems_vector_number vector,
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gic_group *group
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);
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void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets);
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#ifdef RTEMS_SMP
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uint32_t arm_gic_irq_processor_count(void);
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void arm_gic_irq_initialize_secondary_cpu(void);
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */
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