forked from Imagelibrary/rtems
6dee307542
This adds support for the 6 SPI interfaces on the STM32H7 series chips with an initial example for the stm32h750b discovery kit development board. Configuration is similar to existing peripherals. Chip select lines are software-controlled since the SPI peripheral only supports a single hardware-controlled chip select line. This implementation does not use interrupts.
93 lines
3.1 KiB
C
93 lines
3.1 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsARMSTM32H7
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*
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* @brief This source file contains the shared SPI3 peripheral configuration.
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*/
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/*
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* Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stm32h7/hal.h>
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#ifdef SPI3
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/*
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* On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI3 can occupy:
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* AF5:
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* MOSI D6
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* AF6:
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* NSS A4
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* NSS A15
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* SCK B3
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* SCK C10
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* MISO B4
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* MISO C11
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* MOSI C12
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* AF7:
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* MOSI B2
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* MOSI B5
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*/
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stm32h7_spi_context stm32h7_spi3_instance = {
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.spi = {
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.Instance = SPI3,
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/* Configure full-duplex SPI master with 8 bit data size */
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.Init.Mode = SPI_MODE_MASTER,
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.Init.Direction = SPI_DIRECTION_2LINES,
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.Init.DataSize = SPI_DATASIZE_8BIT,
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/* Configure mode 0 */
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.Init.CLKPolarity = SPI_POLARITY_LOW,
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.Init.CLKPhase = SPI_PHASE_1EDGE,
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/* Assume software-controlled-chip-select */
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.Init.NSS = SPI_NSS_SOFT,
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.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
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.Init.FirstBit = SPI_FIRSTBIT_MSB,
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.Init.TIMode = SPI_TIMODE_DISABLE,
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/* Disable CRC calculation */
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.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
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.Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
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.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
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.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
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.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
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.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
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.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
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.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
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.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
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.Init.IOSwap = SPI_IO_SWAP_DISABLE
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},
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.config = &stm32h7_spi3_config,
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.irq = SPI3_IRQn
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};
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#endif /* SPI3 */
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