forked from Imagelibrary/rtems
cb78150d86
This patch updates STM32 H7 HAL source files. The files are taken from two STM projects from their github.com repositories: (i) https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git The project files are still available under BSD-3 license and the version/commit used is: fec141ce999da655a48e1a15db83a72d564a1312 which represents Release v1.11.3 exactly. (ii) https://github.com/STMicroelectronics/cmsis_device_h7.git The project files are available under Apache 2.0 license. Fortunately the project does not contain NOTICE file so no need to do anything special when used in RTEMS. The project version/commit imported is: faccfec37f82f7a1319c21638111b0f7335de7fe which represents Release v1.10.4 exactly.
730 lines
23 KiB
C
730 lines
23 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_ll_rng.h
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* @author MCD Application Team
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* @brief Header file of RNG LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_LL_RNG_H
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#define STM32H7xx_LL_RNG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx.h"
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/** @addtogroup STM32H7xx_LL_Driver
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* @{
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*/
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#if defined (RNG)
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/** @defgroup RNG_LL RNG
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private defines -----------------------------------------------------------*/
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/** @defgroup RNG_LL_Private_Defines RNG Private Defines
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/* Health test control register information to use in CCM algorithm */
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#define LL_RNG_HTCFG 0x17590ABCU /*!< Magic number */
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
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/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/**
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* @brief LL RNG Init Structure Definition
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*/
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typedef struct
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{
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uint32_t ClockErrorDetection; /*!< Clock error detection.
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This parameter can be one value of @ref RNG_LL_CED.
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This parameter can be modified using unitary
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functions @ref LL_RNG_EnableClkErrorDetect(). */
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} LL_RNG_InitTypeDef;
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/** @defgroup RNG_LL_CED Clock Error Detection
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
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#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
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/**
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* @}
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*/
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#if defined(RNG_CR_CONDRST)
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/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
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* @ingroup RTEMSBSPsARMSTM32H7
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* programmable divider acting on the incoming RNG clock
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* @{
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*/
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#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
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#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
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#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
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/**
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* @}
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*/
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/** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
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#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
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/**
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* @}
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*/
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#endif /* RNG_CR_CONDRST */
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/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
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* @ingroup RTEMSBSPsARMSTM32H7
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* @brief Flags defines which can be used with LL_RNG_ReadReg function
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* @{
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*/
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#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
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#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
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#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
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#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
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#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
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/**
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* @}
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*/
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/** @defgroup RNG_LL_EC_IT IT Defines
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* @ingroup RTEMSBSPsARMSTM32H7
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* @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
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* @{
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*/
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#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/**
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* @brief Write a value in RNG register
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* @param __INSTANCE__ RNG Instance
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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/**
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* @brief Read a value in RNG register
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* @param __INSTANCE__ RNG Instance
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/**
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* @brief Enable Random Number Generation
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* @rmtoll CR RNGEN LL_RNG_Enable
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
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{
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SET_BIT(RNGx->CR, RNG_CR_RNGEN);
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}
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/**
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* @brief Disable Random Number Generation
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* @rmtoll CR RNGEN LL_RNG_Disable
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
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{
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CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
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}
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/**
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* @brief Check if Random Number Generator is enabled
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* @rmtoll CR RNGEN LL_RNG_IsEnabled
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* @param RNGx RNG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
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{
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return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable Clock Error Detection
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* @rmtoll CR CED LL_RNG_EnableClkErrorDetect
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
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{
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#if defined(RNG_CR_CONDRST)
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MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
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#else
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CLEAR_BIT(RNGx->CR, RNG_CR_CED);
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#endif /* RNG_CR_CONDRST*/
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}
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/**
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* @brief Disable RNG Clock Error Detection
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* @rmtoll CR CED LL_RNG_DisableClkErrorDetect
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
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{
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#if defined(RNG_CR_CONDRST)
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MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
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#else
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SET_BIT(RNGx->CR, RNG_CR_CED);
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#endif /* RNG_CR_CONDRST*/
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}
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/**
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* @brief Check if RNG Clock Error Detection is enabled
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* @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
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* @param RNGx RNG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
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{
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return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
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}
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#if defined(RNG_CR_CONDRST)
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/**
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* @brief Set RNG Conditioning Soft Reset bit
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* @rmtoll CR CONDRST LL_RNG_EnableCondReset
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
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{
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SET_BIT(RNGx->CR, RNG_CR_CONDRST);
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}
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/**
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* @brief Reset RNG Conditioning Soft Reset bit
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* @rmtoll CR CONDRST LL_RNG_DisableCondReset
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
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{
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
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}
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/**
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* @brief Check if RNG Conditioning Soft Reset bit is set
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* @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset
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* @param RNGx RNG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
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{
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return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable RNG Config Lock
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* @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
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{
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SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
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}
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/**
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* @brief Check if RNG Config Lock is enabled
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* @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
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* @param RNGx RNG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
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{
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return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable NIST Compliance
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* @rmtoll CR NISTC LL_RNG_EnableNistCompliance
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
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{
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MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
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}
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/**
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* @brief Disable NIST Compliance
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* @rmtoll CR NISTC LL_RNG_DisableNistCompliance
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* @param RNGx RNG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
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{
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MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
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}
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/**
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* @brief Check if NIST Compliance is enabled
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* @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance
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* @param RNGx RNG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
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{
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return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
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}
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/**
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* @brief Set RNG Config1 Configuration field value
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* @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
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* @param RNGx RNG Instance
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* @param Config1 Value between 0 and 0x3F
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
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{
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MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
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}
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/**
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* @brief Get RNG Config1 Configuration field value
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* @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
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* @param RNGx RNG Instance
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* @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
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*/
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__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
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{
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return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
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}
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/**
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* @brief Set RNG Config2 Configuration field value
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* @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
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* @param RNGx RNG Instance
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* @param Config2 Value between 0 and 0x7
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
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{
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MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
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}
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/**
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* @brief Get RNG Config2 Configuration field value
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* @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
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* @param RNGx RNG Instance
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* @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
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*/
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__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
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{
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return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
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}
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/**
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* @brief Set RNG Config3 Configuration field value
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* @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
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* @param RNGx RNG Instance
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* @param Config3 Value between 0 and 0xF
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* @retval None
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*/
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__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
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{
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MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
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CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
|
}
|
|
|
|
/**
|
|
* @brief Get RNG Config3 Configuration field value
|
|
* @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
|
|
* @param RNGx RNG Instance
|
|
* @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
|
|
{
|
|
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
|
|
}
|
|
|
|
/**
|
|
* @brief Set RNG Clock divider factor
|
|
* @rmtoll CR CLKDIV LL_RNG_SetClockDivider
|
|
* @param RNGx RNG Instance
|
|
* @param Divider can be one of the following values:
|
|
* @arg @ref LL_RNG_CLKDIV_BY_1
|
|
* @arg @ref LL_RNG_CLKDIV_BY_2
|
|
* @arg @ref LL_RNG_CLKDIV_BY_4
|
|
* @arg @ref LL_RNG_CLKDIV_BY_8
|
|
* @arg @ref LL_RNG_CLKDIV_BY_16
|
|
* @arg @ref LL_RNG_CLKDIV_BY_32
|
|
* @arg @ref LL_RNG_CLKDIV_BY_64
|
|
* @arg @ref LL_RNG_CLKDIV_BY_128
|
|
* @arg @ref LL_RNG_CLKDIV_BY_256
|
|
* @arg @ref LL_RNG_CLKDIV_BY_512
|
|
* @arg @ref LL_RNG_CLKDIV_BY_1024
|
|
* @arg @ref LL_RNG_CLKDIV_BY_2048
|
|
* @arg @ref LL_RNG_CLKDIV_BY_4096
|
|
* @arg @ref LL_RNG_CLKDIV_BY_8192
|
|
* @arg @ref LL_RNG_CLKDIV_BY_16384
|
|
* @arg @ref LL_RNG_CLKDIV_BY_32768
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
|
|
{
|
|
MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
|
|
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
|
|
}
|
|
|
|
/**
|
|
* @brief Get RNG Clock divider factor
|
|
* @rmtoll CR CLKDIV LL_RNG_GetClockDivider
|
|
* @param RNGx RNG Instance
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_RNG_CLKDIV_BY_1
|
|
* @arg @ref LL_RNG_CLKDIV_BY_2
|
|
* @arg @ref LL_RNG_CLKDIV_BY_4
|
|
* @arg @ref LL_RNG_CLKDIV_BY_8
|
|
* @arg @ref LL_RNG_CLKDIV_BY_16
|
|
* @arg @ref LL_RNG_CLKDIV_BY_32
|
|
* @arg @ref LL_RNG_CLKDIV_BY_64
|
|
* @arg @ref LL_RNG_CLKDIV_BY_128
|
|
* @arg @ref LL_RNG_CLKDIV_BY_256
|
|
* @arg @ref LL_RNG_CLKDIV_BY_512
|
|
* @arg @ref LL_RNG_CLKDIV_BY_1024
|
|
* @arg @ref LL_RNG_CLKDIV_BY_2048
|
|
* @arg @ref LL_RNG_CLKDIV_BY_4096
|
|
* @arg @ref LL_RNG_CLKDIV_BY_8192
|
|
* @arg @ref LL_RNG_CLKDIV_BY_16384
|
|
* @arg @ref LL_RNG_CLKDIV_BY_32768
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
|
|
{
|
|
return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
|
|
}
|
|
#endif /* RNG_CR_CONDRST */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Indicate if the RNG Data ready Flag is set or not
|
|
* @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
|
|
* @param RNGx RNG Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
|
|
{
|
|
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Indicate if the Clock Error Current Status Flag is set or not
|
|
* @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
|
|
* @param RNGx RNG Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
|
|
{
|
|
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Indicate if the Seed Error Current Status Flag is set or not
|
|
* @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
|
|
* @param RNGx RNG Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
|
|
{
|
|
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Indicate if the Clock Error Interrupt Status Flag is set or not
|
|
* @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
|
|
* @param RNGx RNG Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
|
|
{
|
|
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Indicate if the Seed Error Interrupt Status Flag is set or not
|
|
* @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
|
|
* @param RNGx RNG Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
|
|
{
|
|
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear Clock Error interrupt Status (CEIS) Flag
|
|
* @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
|
|
* @param RNGx RNG Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
|
|
{
|
|
WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear Seed Error interrupt Status (SEIS) Flag
|
|
* @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
|
|
* @param RNGx RNG Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
|
|
{
|
|
WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RNG_LL_EF_IT_Management IT Management
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable Random Number Generator Interrupt
|
|
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
|
* @rmtoll CR IE LL_RNG_EnableIT
|
|
* @param RNGx RNG Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
|
|
{
|
|
SET_BIT(RNGx->CR, RNG_CR_IE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Random Number Generator Interrupt
|
|
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
|
* @rmtoll CR IE LL_RNG_DisableIT
|
|
* @param RNGx RNG Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
|
|
{
|
|
CLEAR_BIT(RNGx->CR, RNG_CR_IE);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Random Number Generator Interrupt is enabled
|
|
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
|
* @rmtoll CR IE LL_RNG_IsEnabledIT
|
|
* @param RNGx RNG Instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
|
|
{
|
|
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RNG_LL_EF_Data_Management Data Management
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Return32-bit Random Number value
|
|
* @rmtoll DR RNDATA LL_RNG_ReadRandData32
|
|
* @param RNGx RNG Instance
|
|
* @retval Generated 32-bit random value
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
|
|
{
|
|
return (uint32_t)(READ_REG(RNGx->DR));
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
|
|
/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Set RNG Health Test Control
|
|
* @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig
|
|
* @param RNGx RNG Instance
|
|
* @param HTCFG can be values of 32 bits
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
|
|
{
|
|
/*!< magic number must be written immediately before to RNG_HTCRG */
|
|
WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
|
|
|
|
WRITE_REG(RNGx->HTCR, HTCFG);
|
|
}
|
|
|
|
/**
|
|
* @brief Get RNG Health Test Control
|
|
* @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig
|
|
* @param RNGx RNG Instance
|
|
* @retval Return 32-bit RNG Health Test configuration
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
|
|
{
|
|
/*!< magic number must be written immediately before reading RNG_HTCRG */
|
|
WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
|
|
|
|
return (uint32_t)READ_REG(RNGx->HTCR);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */
|
|
#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
|
|
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
|
|
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
|
|
ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* RNG */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32H7xx_LL_RNG_H */
|
|
|