forked from Imagelibrary/rtems
cb78150d86
This patch updates STM32 H7 HAL source files. The files are taken from two STM projects from their github.com repositories: (i) https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git The project files are still available under BSD-3 license and the version/commit used is: fec141ce999da655a48e1a15db83a72d564a1312 which represents Release v1.11.3 exactly. (ii) https://github.com/STMicroelectronics/cmsis_device_h7.git The project files are available under Apache 2.0 license. Fortunately the project does not contain NOTICE file so no need to do anything special when used in RTEMS. The project version/commit imported is: faccfec37f82f7a1319c21638111b0f7335de7fe which represents Release v1.10.4 exactly.
833 lines
36 KiB
C
833 lines
36 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_hal_lptim.h
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* @author MCD Application Team
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* @brief Header file of LPTIM HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_HAL_LPTIM_H
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#define STM32H7xx_HAL_LPTIM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal_def.h"
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{
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*/
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#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
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/** @addtogroup LPTIM
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/**
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* @brief LPTIM Clock configuration definition
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*/
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typedef struct
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{
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uint32_t Source; /*!< Selects the clock source.
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This parameter can be a value of @ref LPTIM_Clock_Source */
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uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
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This parameter can be a value of @ref LPTIM_Clock_Prescaler */
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} LPTIM_ClockConfigTypeDef;
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/**
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* @brief LPTIM Clock configuration definition
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*/
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typedef struct
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{
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uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
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if the ULPTIM input is selected.
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Note: This parameter is used only when Ultra low power clock source is used.
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Note: If the polarity is configured on 'both edges', an auxiliary clock
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(one of the Low power oscillator) must be active.
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This parameter can be a value of @ref LPTIM_Clock_Polarity */
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uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
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Note: This parameter is used only when Ultra low power clock source is used.
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This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
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} LPTIM_ULPClockConfigTypeDef;
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/**
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* @brief LPTIM Trigger configuration definition
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*/
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typedef struct
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{
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uint32_t Source; /*!< Selects the Trigger source.
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This parameter can be a value of @ref LPTIM_Trigger_Source */
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uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
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Note: This parameter is used only when an external trigger is used.
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This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
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uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
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Note: This parameter is used only when an external trigger is used.
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This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
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} LPTIM_TriggerConfigTypeDef;
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/**
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* @brief LPTIM Initialization Structure definition
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*/
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typedef struct
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{
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LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
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LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
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LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
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uint32_t OutputPolarity; /*!< Specifies the Output polarity.
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This parameter can be a value of @ref LPTIM_Output_Polarity */
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uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
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values is done immediately or after the end of current period.
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This parameter can be a value of @ref LPTIM_Updating_Mode */
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uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
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or each external event.
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This parameter can be a value of @ref LPTIM_Counter_Source */
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uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
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This parameter can be a value of @ref LPTIM_Input1_Source */
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uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
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Note: This parameter is used only for encoder feature so is used only
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for LPTIM1 instance.
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This parameter can be a value of @ref LPTIM_Input2_Source */
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} LPTIM_InitTypeDef;
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/**
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* @brief HAL LPTIM State structure definition
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*/
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typedef enum
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{
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HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
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HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
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HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
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HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
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HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
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} HAL_LPTIM_StateTypeDef;
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/**
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* @brief LPTIM handle Structure definition
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*/
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#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
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typedef struct __LPTIM_HandleTypeDef
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#else
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typedef struct
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#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
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{
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LPTIM_TypeDef *Instance; /*!< Register base address */
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LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
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HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
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HAL_LockTypeDef Lock; /*!< LPTIM locking object */
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__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
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#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
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void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
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void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
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void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
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void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
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void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
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void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
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void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
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void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
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void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
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#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
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} LPTIM_HandleTypeDef;
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#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
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/**
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* @brief HAL LPTIM Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
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HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
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HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
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HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
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HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
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HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
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HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
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HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
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HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
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} HAL_LPTIM_CallbackIDTypeDef;
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/**
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* @brief HAL TIM Callback pointer definition
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*/
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typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
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#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
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#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
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/**
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* @}
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*/
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/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_PRESCALER_DIV1 0x00000000U
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#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
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#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
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#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
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#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
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#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
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#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
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#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
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/**
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* @}
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*/
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/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
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#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
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/**
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* @}
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*/
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/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
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#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
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#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
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#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
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/**
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* @}
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*/
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/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
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#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
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#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
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/**
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* @}
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*/
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/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
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#define LPTIM_TRIGSOURCE_0 0x00000000U
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#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
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#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
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#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
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#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
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#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
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#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
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#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
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/**
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* @}
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*/
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/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
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#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
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#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
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/**
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* @}
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*/
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/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
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#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
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#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
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#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
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/**
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* @}
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*/
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/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
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#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
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/**
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* @}
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*/
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/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
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#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
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/**
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* @}
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*/
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/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
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#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
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#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM2 */
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#define LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
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#define LPTIM_INPUT1SOURCE_NOT_CONNECTED 0x00000000U /*!< For LPTIM3 */
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#define LPTIM_INPUT1SOURCE_SAI4_FSA LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM3 */
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#define LPTIM_INPUT1SOURCE_SAI4_FSB LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM3 */
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/**
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* @}
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*/
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/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 */
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#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 */
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/**
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* @}
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*/
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/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
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#define LPTIM_FLAG_UP LPTIM_ISR_UP
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#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
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#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
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#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
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#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
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#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
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/**
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* @}
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*/
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/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
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#define LPTIM_IT_UP LPTIM_IER_UPIE
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#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
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#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
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#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
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#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
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#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros -----------------------------------------------------------*/
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/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
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* @ingroup RTEMSBSPsARMSTM32H7
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* @{
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*/
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/** @brief Reset LPTIM handle state.
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* @param __HANDLE__ LPTIM handle
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* @retval None
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*/
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#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
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#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
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(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
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(__HANDLE__)->MspInitCallback = NULL; \
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(__HANDLE__)->MspDeInitCallback = NULL; \
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} while(0)
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#else
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#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
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#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
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/**
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* @brief Enable the LPTIM peripheral.
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* @param __HANDLE__ LPTIM handle
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* @retval None
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*/
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#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
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/**
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* @brief Disable the LPTIM peripheral.
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* @param __HANDLE__ LPTIM handle
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* @note The following sequence is required to solve LPTIM disable HW limitation.
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* Please check Errata Sheet ES0335 for more details under "MCU may remain
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* stuck in LPTIM interrupt when entering Stop mode" section.
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* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
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* check for TIMEOUT.
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* @retval None
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*/
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#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
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/**
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* @brief Start the LPTIM peripheral in Continuous mode.
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* @param __HANDLE__ LPTIM handle
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* @retval None
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*/
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#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
|
|
/**
|
|
* @brief Start the LPTIM peripheral in single mode.
|
|
* @param __HANDLE__ LPTIM handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
|
|
|
|
/**
|
|
* @brief Reset the LPTIM Counter register in synchronous mode.
|
|
* @param __HANDLE__ LPTIM handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
|
|
|
|
/**
|
|
* @brief Reset after read of the LPTIM Counter register in asynchronous mode.
|
|
* @param __HANDLE__ LPTIM handle
|
|
* @retval None
|
|
*/
|
|
#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
|
|
|
|
/**
|
|
* @brief Write the passed parameter in the Autoreload register.
|
|
* @param __HANDLE__ LPTIM handle
|
|
* @param __VALUE__ Autoreload value
|
|
* This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
|
|
* @retval None
|
|
* @note The ARR register can only be modified when the LPTIM instance is enabled.
|
|
*/
|
|
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
|
|
|
|
/**
|
|
* @brief Write the passed parameter in the Compare register.
|
|
* @param __HANDLE__ LPTIM handle
|
|
* @param __VALUE__ Compare value
|
|
* @retval None
|
|
* @note The CMP register can only be modified when the LPTIM instance is enabled.
|
|
*/
|
|
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
|
|
|
|
/**
|
|
* @brief Check whether the specified LPTIM flag is set or not.
|
|
* @param __HANDLE__ LPTIM handle
|
|
* @param __FLAG__ LPTIM flag to check
|
|
* This parameter can be a value of:
|
|
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
|
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
|
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
|
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
|
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
|
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
|
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
|
* @retval The state of the specified flag (SET or RESET).
|
|
*/
|
|
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
|
|
|
|
/**
|
|
* @brief Clear the specified LPTIM flag.
|
|
* @param __HANDLE__ LPTIM handle.
|
|
* @param __FLAG__ LPTIM flag to clear.
|
|
* This parameter can be a value of:
|
|
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
|
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
|
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
|
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
|
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
|
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
|
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
|
* @retval None.
|
|
*/
|
|
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
|
|
|
/**
|
|
* @brief Enable the specified LPTIM interrupt.
|
|
* @param __HANDLE__ LPTIM handle.
|
|
* @param __INTERRUPT__ LPTIM interrupt to set.
|
|
* This parameter can be a value of:
|
|
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
|
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
|
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
|
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
|
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
|
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
|
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
|
* @retval None.
|
|
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
|
|
*/
|
|
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the specified LPTIM interrupt.
|
|
* @param __HANDLE__ LPTIM handle.
|
|
* @param __INTERRUPT__ LPTIM interrupt to set.
|
|
* This parameter can be a value of:
|
|
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
|
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
|
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
|
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
|
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
|
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
|
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
|
* @retval None.
|
|
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
|
|
*/
|
|
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Check whether the specified LPTIM interrupt source is enabled or not.
|
|
* @param __HANDLE__ LPTIM handle.
|
|
* @param __INTERRUPT__ LPTIM interrupt to check.
|
|
* This parameter can be a value of:
|
|
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
|
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
|
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
|
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
|
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
|
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
|
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
|
* @retval Interrupt status.
|
|
*/
|
|
|
|
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
|
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup LPTIM_Exported_Functions_Group1
|
|
* @brief Initialization and Configuration functions.
|
|
* @{
|
|
*/
|
|
/* Initialization/de-initialization functions ********************************/
|
|
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
|
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* MSP functions *************************************************************/
|
|
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
|
|
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup LPTIM_Exported_Functions_Group2
|
|
* @brief Start-Stop operation functions.
|
|
* @{
|
|
*/
|
|
/* Start/Stop operation functions *********************************************/
|
|
/* ################################# PWM Mode ################################*/
|
|
/* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
/* Non-Blocking mode: Interrupt */
|
|
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* ############################# One Pulse Mode ##############################*/
|
|
/* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
/* Non-Blocking mode: Interrupt */
|
|
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* ############################## Set once Mode ##############################*/
|
|
/* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
/* Non-Blocking mode: Interrupt */
|
|
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* ############################### Encoder Mode ##############################*/
|
|
/* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
/* Non-Blocking mode: Interrupt */
|
|
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* ############################# Time out Mode ##############################*/
|
|
/* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
|
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
/* Non-Blocking mode: Interrupt */
|
|
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
|
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* ############################## Counter Mode ###############################*/
|
|
/* Blocking mode: Polling */
|
|
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
/* Non-Blocking mode: Interrupt */
|
|
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup LPTIM_Exported_Functions_Group3
|
|
* @brief Read operation functions.
|
|
* @{
|
|
*/
|
|
/* Reading operation functions ************************************************/
|
|
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
|
|
uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
|
|
uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup LPTIM_Exported_Functions_Group4
|
|
* @brief LPTIM IRQ handler and callback functions.
|
|
* @{
|
|
*/
|
|
/* LPTIM IRQ functions *******************************************************/
|
|
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* CallBack functions ********************************************************/
|
|
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
|
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
|
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
|
|
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
|
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
|
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
|
|
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
|
|
|
/* Callbacks Register/UnRegister functions ***********************************/
|
|
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
|
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
|
|
pLPTIM_CallbackTypeDef pCallback);
|
|
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
|
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup LPTIM_Group5
|
|
* @brief Peripheral State functions.
|
|
* @{
|
|
*/
|
|
/* Peripheral State functions ************************************************/
|
|
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private types -------------------------------------------------------------*/
|
|
/** @defgroup LPTIM_Private_Types LPTIM Private Types
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private variables ---------------------------------------------------------*/
|
|
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private constants ---------------------------------------------------------*/
|
|
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private macros ------------------------------------------------------------*/
|
|
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
|
|
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
|
|
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
|
|
|
|
|
|
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
|
|
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
|
|
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
|
|
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
|
|
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
|
|
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
|
|
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
|
|
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
|
|
|
|
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
|
|
|
|
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
|
|
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
|
|
|
|
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
|
|
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
|
|
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
|
|
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
|
|
|
|
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
|
|
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
|
|
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
|
|
|
|
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
|
|
((__TRIG__) == LPTIM_TRIGSOURCE_7))
|
|
|
|
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
|
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
|
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
|
|
|
|
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
|
|
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
|
|
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
|
|
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
|
|
|
|
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
|
|
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
|
|
|
|
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
|
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
|
|
|
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
|
|
|
|
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
|
|
((__PERIOD__) <= 0x0000FFFFUL))
|
|
|
|
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
|
|
|
|
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
|
((((__INSTANCE__) == LPTIM1) && \
|
|
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
|
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|
|
|| \
|
|
(((__INSTANCE__) == LPTIM2) && \
|
|
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
|
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
|
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
|
|
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
|
|
|| \
|
|
(((__INSTANCE__) == LPTIM3) && \
|
|
(((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) || \
|
|
((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSA) || \
|
|
((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSB))))
|
|
|
|
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
|
((((__INSTANCE__) == LPTIM1) || \
|
|
((__INSTANCE__) == LPTIM2)) && \
|
|
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
|
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
|
* @ingroup RTEMSBSPsARMSTM32H7
|
|
* @{
|
|
*/
|
|
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
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#endif /* STM32H7xx_HAL_LPTIM_H */
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