forked from Imagelibrary/rtems
094355d4f1
The nocache-memory was set as device memory. It's not necessary to be that strict. Set it to normal non-cacheable non-shareable memory instead.
82 lines
3.2 KiB
C
82 lines
3.2 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2020 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <imxrt/memory.h>
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#include <imxrt/mpu-config.h>
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#include <rtems/score/armv7m.h>
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BSP_START_DATA_SECTION const ARMV7M_MPU_Region_config
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imxrt_config_mpu_region [] = {
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{
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.begin = imxrt_memory_extram_begin,
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.end = imxrt_memory_extram_end,
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.rasr = ARMV7M_MPU_RASR_AP(0x3)
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| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
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| ARMV7M_MPU_RASR_ENABLE,
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}, {
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.begin = imxrt_memory_ocram_begin,
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.end = imxrt_memory_ocram_end,
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.rasr = ARMV7M_MPU_RASR_AP(0x3)
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| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
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| ARMV7M_MPU_RASR_ENABLE,
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}, {
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.begin = imxrt_memory_flash_raw_begin,
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.end = imxrt_memory_flash_raw_end,
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.rasr = ARMV7M_MPU_RASR_AP(0x3)
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| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
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| ARMV7M_MPU_RASR_ENABLE,
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}, {
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.begin = imxrt_memory_extram_nocache_begin,
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.end = imxrt_memory_extram_nocache_end,
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.rasr = ARMV7M_MPU_RASR_AP(0x3)
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| ARMV7M_MPU_RASR_TEX(0x1)
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| ARMV7M_MPU_RASR_ENABLE,
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}, {
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.begin = imxrt_memory_ocram_nocache_begin,
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.end = imxrt_memory_ocram_nocache_end,
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.rasr = ARMV7M_MPU_RASR_AP(0x3)
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| ARMV7M_MPU_RASR_TEX(0x1)
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| ARMV7M_MPU_RASR_ENABLE,
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}, {
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.begin = imxrt_memory_peripheral_begin,
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.end = imxrt_memory_peripheral_end,
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.rasr = ARMV7M_MPU_RASR_XN
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| ARMV7M_MPU_RASR_AP(0x3)
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| ARMV7M_MPU_RASR_TEX(0x2)
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| ARMV7M_MPU_RASR_ENABLE,
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}, {
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.begin = imxrt_memory_null_begin,
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.end = imxrt_memory_null_end,
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.rasr = ARMV7M_MPU_RASR_XN
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| ARMV7M_MPU_RASR_AP(0x0)
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| ARMV7M_MPU_RASR_ENABLE,
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}
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};
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BSP_START_DATA_SECTION const size_t imxrt_config_mpu_region_count =
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RTEMS_ARRAY_SIZE(imxrt_config_mpu_region);
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