forked from Imagelibrary/rtems
432 lines
10 KiB
C
432 lines
10 KiB
C
/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief Support for the BeagleBone Black.
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*/
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/**
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* Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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/* BSP specific function definitions for BeagleBone Black.
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* It is totally beased on Generic GPIO API definition.
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* For more details related to GPIO API please have a
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* look at libbbsp/shared/include/gpio.h
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*/
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#include <bsp/beagleboneblack.h>
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#include <bsp/irq-generic.h>
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#include <bsp/gpio.h>
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#include <bsp/bbb-gpio.h>
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#include <libcpu/am335x.h>
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#include <assert.h>
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#include <stdlib.h>
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/* Currently these definitions are for BeagleBone Black board only
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* Later on Beagle-xM board support can be added in this code.
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* After support gets added if condition should be removed
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*/
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#if IS_AM335X
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static const uint32_t gpio_bank_addrs[] =
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{ AM335X_GPIO0_BASE,
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AM335X_GPIO1_BASE,
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AM335X_GPIO2_BASE,
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AM335X_GPIO3_BASE };
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static const rtems_vector_number gpio_bank_vector[] =
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{ AM335X_INT_GPIOINT0A,
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AM335X_INT_GPIOINT1A,
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AM335X_INT_GPIOINT2A,
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AM335X_INT_GPIOINT3A };
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/* Get the value of Base Register + Offset */
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uint32_t static inline bbb_reg(uint32_t bank, uint32_t reg)
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{
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return (gpio_bank_addrs[bank] + reg);
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}
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static rtems_status_code bbb_select_pin_function(
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uint32_t bank,
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uint32_t pin,
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uint32_t type
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) {
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if ( type == BBB_DIGITAL_IN ) {
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mmio_set(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin));
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} else {
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mmio_clear(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin));
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask)
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{
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mmio_set(bbb_reg(bank, AM335X_GPIO_SETDATAOUT), bitmask);
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask)
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{
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mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), bitmask);
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return RTEMS_SUCCESSFUL;
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}
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uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask)
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{
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return (bbb_reg(bank, AM335X_GPIO_DATAIN) & bitmask);
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}
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rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin)
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{
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mmio_set(bbb_reg(bank, AM335X_GPIO_SETDATAOUT), BIT(pin));
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin)
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{
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mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), BIT(pin));
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return RTEMS_SUCCESSFUL;
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}
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uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin)
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{
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return (mmio_read(bbb_reg(bank, AM335X_GPIO_DATAIN)) & BIT(pin));
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}
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rtems_status_code rtems_gpio_bsp_select_input(
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uint32_t bank,
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uint32_t pin,
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void *bsp_specific
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) {
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return bbb_select_pin_function(bank, pin, BBB_DIGITAL_IN);
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}
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rtems_status_code rtems_gpio_bsp_select_output(
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uint32_t bank,
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uint32_t pin,
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void *bsp_specific
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) {
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return bbb_select_pin_function(bank, pin, BBB_DIGITAL_OUT);
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}
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rtems_status_code rtems_gpio_bsp_select_specific_io(
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uint32_t bank,
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uint32_t pin,
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uint32_t function,
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void *pin_data
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_set_resistor_mode(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_pull_mode mode
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) {
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/* TODO: Add support for setting up resistor mode */
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return RTEMS_NOT_DEFINED;
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}
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rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank)
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{
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return gpio_bank_vector[bank];
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}
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uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector)
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{
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uint32_t event_status;
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uint8_t bank_nr = 0;
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/* Following loop will get the bank number from vector number */
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while (bank_nr < GPIO_BANK_COUNT && vector != gpio_bank_vector[bank_nr])
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{
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bank_nr++;
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}
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/* Retrieve the interrupt event status. */
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event_status = mmio_read(bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0));
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/* Clear the interrupt line. */
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mmio_write(
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(bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0)), event_status);
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return event_status;
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}
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rtems_status_code rtems_gpio_bsp_enable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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/* Enable IRQ generation for the specific pin */
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mmio_set(bbb_reg(bank, AM335X_GPIO_IRQSTATUS_SET_0), BIT(pin));
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switch ( interrupt ) {
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case FALLING_EDGE:
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/* Enables asynchronous falling edge detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
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break;
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case RISING_EDGE:
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/* Enables asynchronous rising edge detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
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break;
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case BOTH_EDGES:
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/* Enables asynchronous falling edge detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
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/* Enables asynchronous rising edge detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
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break;
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case LOW_LEVEL:
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/* Enables pin low level detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
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break;
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case HIGH_LEVEL:
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/* Enables pin high level detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
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break;
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case BOTH_LEVELS:
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/* Enables pin low level detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
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/* Enables pin high level detection. */
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mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
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break;
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case NONE:
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default:
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return RTEMS_UNSATISFIED;
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}
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/* The detection starts after 5 clock cycles as per AM335X TRM
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* This period is required to clean the synchronization edge/
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* level detection pipeline
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*/
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asm volatile("nop"); asm volatile("nop"); asm volatile("nop");
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asm volatile("nop"); asm volatile("nop");
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_disable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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/* Clear IRQ generation for the specific pin */
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mmio_write(bbb_reg(bank, AM335X_GPIO_IRQSTATUS_CLR_0), BIT(pin));
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switch ( interrupt ) {
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case FALLING_EDGE:
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/* Disables asynchronous falling edge detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
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break;
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case RISING_EDGE:
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/* Disables asynchronous rising edge detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
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break;
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case BOTH_EDGES:
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/* Disables asynchronous falling edge detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
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/* Disables asynchronous rising edge detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
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break;
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case LOW_LEVEL:
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/* Disables pin low level detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
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break;
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case HIGH_LEVEL:
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/* Disables pin high level detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
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break;
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case BOTH_LEVELS:
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/* Disables pin low level detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
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/* Disables pin high level detection. */
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mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
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break;
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case NONE:
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default:
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return RTEMS_UNSATISFIED;
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}
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/* The detection starts after 5 clock cycles as per AM335X TRM
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* This period is required to clean the synchronization edge/
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* level detection pipeline
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*/
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asm volatile("nop"); asm volatile("nop"); asm volatile("nop");
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asm volatile("nop"); asm volatile("nop");
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_multi_select(
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rtems_gpio_multiple_pin_select *pins,
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uint32_t pin_count,
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uint32_t select_bank
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) {
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uint32_t register_address;
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uint32_t select_register;
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uint8_t i;
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register_address = gpio_bank_addrs[select_bank] + AM335X_GPIO_OE;
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select_register = REG(register_address);
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for ( i = 0; i < pin_count; ++i ) {
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if ( pins[i].function == DIGITAL_INPUT ) {
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select_register |= BIT(pins[i].pin_number);
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} else if ( pins[i].function == DIGITAL_OUTPUT ) {
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select_register &= ~BIT(pins[i].pin_number);
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} else { /* BSP_SPECIFIC function. */
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return RTEMS_NOT_DEFINED;
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}
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}
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REG(register_address) = select_register;
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_specific_group_operation(
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uint32_t bank,
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uint32_t *pins,
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uint32_t pin_count,
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void *arg
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) {
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return RTEMS_NOT_DEFINED;
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}
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#endif /* IS_AM335X */
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/* For support of BeagleboardxM */
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#if IS_DM3730
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/* Currently this section is just to satisfy
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* GPIO API and to make the build successful.
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* Later on support can be added here.
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*/
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rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask)
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{
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask)
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{
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return RTEMS_NOT_DEFINED;
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}
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uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask)
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{
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return -1;
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}
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rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin)
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{
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin)
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{
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return RTEMS_NOT_DEFINED;
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}
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uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin)
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{
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return -1;
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}
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rtems_status_code rtems_gpio_bsp_select_input(
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uint32_t bank,
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uint32_t pin,
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void *bsp_specific
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_select_output(
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uint32_t bank,
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uint32_t pin,
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void *bsp_specific
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_select_specific_io(
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uint32_t bank,
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uint32_t pin,
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uint32_t function,
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void *pin_data
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_set_resistor_mode(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_pull_mode mode
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank)
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{
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return -1;
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}
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uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector)
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{
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return -1;
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}
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rtems_status_code rtems_gpio_bsp_enable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_disable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_multi_select(
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rtems_gpio_multiple_pin_select *pins,
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uint32_t pin_count,
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uint32_t select_bank
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_specific_group_operation(
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uint32_t bank,
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uint32_t *pins,
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uint32_t pin_count,
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void *arg
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) {
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return RTEMS_NOT_DEFINED;
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}
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#endif /* IS_DM3730 */
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