forked from Imagelibrary/rtems
1eed6f8bfc
Pass the parameter of the clock interrupt handler to Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes it possible to use the interrupt handler argument in clock drivers. Use the interrupt handler provided by Clock_driver_support_install_isr() to avoid local delarations of Clock_isr(). Update #4862.
300 lines
8.0 KiB
C
300 lines
8.0 KiB
C
/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief Clock driver configuration.
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*/
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/*
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* Copyright (c) 2014 Ben Gras <beng@shrike-systems.com>.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <rtems/timecounter.h>
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#include <bsp.h>
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#include <libcpu/omap_timer.h>
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static struct timecounter beagle_clock_tc;
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static omap_timer_registers_t regs_v1 = {
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.TIDR = OMAP3_TIMER_TIDR,
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.TIOCP_CFG = OMAP3_TIMER_TIOCP_CFG,
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.TISTAT = OMAP3_TIMER_TISTAT,
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.TISR = OMAP3_TIMER_TISR,
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.TIER = OMAP3_TIMER_TIER,
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.TWER = OMAP3_TIMER_TWER,
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.TCLR = OMAP3_TIMER_TCLR,
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.TCRR = OMAP3_TIMER_TCRR,
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.TLDR = OMAP3_TIMER_TLDR,
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.TTGR = OMAP3_TIMER_TTGR,
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.TWPS = OMAP3_TIMER_TWPS,
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.TMAR = OMAP3_TIMER_TMAR,
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.TCAR1 = OMAP3_TIMER_TCAR1,
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.TSICR = OMAP3_TIMER_TSICR,
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.TCAR2 = OMAP3_TIMER_TCAR2,
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.TPIR = OMAP3_TIMER_TPIR,
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.TNIR = OMAP3_TIMER_TNIR,
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.TCVR = OMAP3_TIMER_TCVR,
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.TOCR = OMAP3_TIMER_TOCR,
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.TOWR = OMAP3_TIMER_TOWR,
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};
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#if IS_AM335X
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/* AM335X has a different ip block for the non 1ms timers */
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static omap_timer_registers_t regs_v2 = {
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.TIDR = AM335X_TIMER_TIDR,
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.TIOCP_CFG = AM335X_TIMER_TIOCP_CFG,
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.TISTAT = AM335X_TIMER_IRQSTATUS_RAW,
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.TISR = AM335X_TIMER_IRQSTATUS,
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.TIER = AM335X_TIMER_IRQENABLE_SET,
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.TWER = AM335X_TIMER_IRQWAKEEN,
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.TCLR = AM335X_TIMER_TCLR,
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.TCRR = AM335X_TIMER_TCRR,
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.TLDR = AM335X_TIMER_TLDR,
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.TTGR = AM335X_TIMER_TTGR,
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.TWPS = AM335X_TIMER_TWPS,
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.TMAR = AM335X_TIMER_TMAR,
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.TCAR1 = AM335X_TIMER_TCAR1,
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.TSICR = AM335X_TIMER_TSICR,
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.TCAR2 = AM335X_TIMER_TCAR2,
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.TPIR = -1, /* UNDEF */
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.TNIR = -1, /* UNDEF */
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.TCVR = -1, /* UNDEF */
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.TOCR = -1, /* UNDEF */
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.TOWR = -1 /* UNDEF */
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};
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#endif
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/* which timers are in use? target-dependent.
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* initialize at compile time.
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*/
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#if IS_DM3730
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static omap_timer_t dm37xx_timer = {
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.base = OMAP3_GPTIMER1_BASE,
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.irq_nr = OMAP3_GPT1_IRQ,
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.regs = ®s_v1
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};
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/* free running timer */
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static omap_timer_t dm37xx_fr_timer = {
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.base = OMAP3_GPTIMER10_BASE,
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.irq_nr = OMAP3_GPT10_IRQ,
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.regs = ®s_v1
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};
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static struct omap_timer *fr_timer = &dm37xx_fr_timer;
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static struct omap_timer *timer = &dm37xx_timer;
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#endif
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#if IS_AM335X
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/* normal timer */
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static omap_timer_t am335x_timer = {
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.base = AM335X_DMTIMER1_1MS_BASE,
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.irq_nr = AM335X_INT_TINT1_1MS,
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.regs = ®s_v1
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};
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/* free running timer */
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static omap_timer_t am335x_fr_timer = {
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.base = AM335X_DMTIMER7_BASE,
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.irq_nr = AM335X_INT_TINT7,
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.regs = ®s_v2
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};
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static struct omap_timer *fr_timer = &am335x_fr_timer;
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static struct omap_timer *timer = &am335x_timer;
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#endif
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#if IS_AM335X
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#define FRCLOCK_HZ (16*1500000)
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#endif
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#if IS_DM3730
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#define FRCLOCK_HZ (8*1625000)
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#endif
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#ifndef FRCLOCK_HZ
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#error expected IS_AM335X or IS_DM3730 to be defined.
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#endif
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static void
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omap3_frclock_init(void)
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{
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uint32_t tisr;
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#if IS_DM3730
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/* Stop timer */
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mmio_clear(fr_timer->base + fr_timer->regs->TCLR,
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OMAP3_TCLR_ST);
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/* Use functional clock source for GPTIMER10 */
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mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
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#endif
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#if IS_AM335X
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/* Disable the module and wait for the module to be disabled */
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set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,
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CM_MODULEMODE_DISABLED);
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while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST)
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!= CM_CLKCTRL_IDLEST_DISABLE);
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set32(CLKSEL_TIMER7_CLK, CLKSEL_TIMER7_CLK_SEL_MASK,
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CLKSEL_TIMER7_CLK_SEL_SEL2);
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while ((read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK)
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!= CLKSEL_TIMER7_CLK_SEL_SEL2);
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/* enable the module and wait for the module to be ready */
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set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,
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CM_MODULEMODE_ENABLE);
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while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST)
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!= CM_CLKCTRL_IDLEST_FUNC);
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/* Stop timer */
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mmio_clear(fr_timer->base + fr_timer->regs->TCLR,
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OMAP3_TCLR_ST);
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#endif
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/* Start and auto-reload at 0 */
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mmio_write(fr_timer->base + fr_timer->regs->TLDR, 0x0);
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mmio_write(fr_timer->base + fr_timer->regs->TCRR, 0x0);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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/* Clear interrupt status */
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mmio_write(fr_timer->base + fr_timer->regs->TISR, tisr);
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mmio_write(fr_timer->base + fr_timer->regs->TIER,
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OMAP3_TIER_OVF_IT_ENA);
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/* Start timer, without prescaler */
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mmio_set(fr_timer->base + fr_timer->regs->TCLR,
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OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST);
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}
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static uint32_t
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beagle_clock_get_timecount(struct timecounter *tc)
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{
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return mmio_read(fr_timer->base + fr_timer->regs->TCRR);
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}
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static void
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beagle_clock_initialize(void)
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{
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uint32_t freq = 1000000UL/rtems_configuration_get_microseconds_per_tick();
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/* we only support 1ms resolution */
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uint32_t tisr;
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#if IS_DM3730
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/* Stop timer */
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mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST);
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/* Use 32 KHz clock source for GPTIMER1 */
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mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1);
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#endif
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#if IS_AM335X
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/* disable the module and wait for the module to be disabled */
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set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK,
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CM_MODULEMODE_DISABLED);
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while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST)
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!= CM_CLKCTRL_IDLEST_DISABLE);
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set32(CLKSEL_TIMER1MS_CLK, CLKSEL_TIMER1MS_CLK_SEL_MASK,
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CLKSEL_TIMER1MS_CLK_SEL_SEL2);
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while ((read32(CLKSEL_TIMER1MS_CLK) &
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CLKSEL_TIMER1MS_CLK_SEL_MASK) !=
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CLKSEL_TIMER1MS_CLK_SEL_SEL2);
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/* enable the module and wait for the module to be ready */
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set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK,
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CM_MODULEMODE_ENABLE);
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while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST)
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!= CM_CLKCTRL_IDLEST_FUNC);
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/* Stop timer */
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mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST);
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#endif
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/* Use 1-ms tick mode for GPTIMER1 TRM 16.2.4.2.1 */
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mmio_write(timer->base + timer->regs->TPIR, 232000);
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mmio_write(timer->base + timer->regs->TNIR, -768000);
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mmio_write(timer->base + timer->regs->TLDR,
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0xffffffff - (32768 / freq) + 1);
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mmio_write(timer->base + timer->regs->TCRR,
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0xffffffff - (32768 / freq) + 1);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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/* Clear interrupt status */
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mmio_write(timer->base + timer->regs->TISR, tisr);
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mmio_write(timer->base + timer->regs->TIER, OMAP3_TIER_OVF_IT_ENA);
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/* Start timer */
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mmio_set(timer->base + timer->regs->TCLR,
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OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST);
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/* also initilize the free runnning timer */
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omap3_frclock_init();
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#if IS_AM335X
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/* Disable AM335X watchdog */
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mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0xAAAA);
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while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
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mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0x5555);
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while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ;
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#endif
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/* Install timecounter */ \
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beagle_clock_tc.tc_get_timecount = beagle_clock_get_timecount;
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beagle_clock_tc.tc_counter_mask = 0xffffffff;
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beagle_clock_tc.tc_frequency = FRCLOCK_HZ;
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beagle_clock_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
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rtems_timecounter_install(&beagle_clock_tc);
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}
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static void beagle_clock_at_tick(void)
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{
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mmio_write(timer->base + timer->regs->TISR,
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OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG);
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}
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static rtems_interrupt_handler clock_isr = NULL;
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static void beagle_clock_handler_install(rtems_interrupt_handler isr)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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sc = rtems_interrupt_handler_install(
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timer->irq_nr,
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"Clock",
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RTEMS_INTERRUPT_UNIQUE,
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isr,
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NULL
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);
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if (sc != RTEMS_SUCCESSFUL) {
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rtems_fatal_error_occurred(0xdeadbeef);
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}
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clock_isr = isr;
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}
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#define Clock_driver_support_at_tick(arg) beagle_clock_at_tick()
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#define Clock_driver_support_initialize_hardware() beagle_clock_initialize()
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#define Clock_driver_support_install_isr(isr) \
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beagle_clock_handler_install(isr)
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/* Include shared source clock driver code */
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#include "../../shared/dev/clock/clockimpl.h"
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