forked from Imagelibrary/rtems
99 lines
3.0 KiB
ArmAsm
99 lines
3.0 KiB
ArmAsm
/*
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* Copyright (c) 2018 embedded brains GmbH
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*
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* Copyright (c) 2015 University of York.
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* Hesham ALmatary <hesham@alumni.york.ac.uk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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.section .text, "ax", @progbits
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.align 2
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PUBLIC(_CPU_Context_switch)
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PUBLIC(_CPU_Context_restore)
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PUBLIC(_CPU_Context_restore_fp)
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PUBLIC(_CPU_Context_save_fp)
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SYM(_CPU_Context_switch):
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GET_SELF_CPU_CONTROL a2
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lw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
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SREG ra, RISCV_CONTEXT_RA(a0)
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SREG sp, RISCV_CONTEXT_SP(a0)
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SREG s0, RISCV_CONTEXT_S0(a0)
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SREG s1, RISCV_CONTEXT_S1(a0)
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SREG s2, RISCV_CONTEXT_S2(a0)
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SREG s3, RISCV_CONTEXT_S3(a0)
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SREG s4, RISCV_CONTEXT_S4(a0)
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SREG s5, RISCV_CONTEXT_S5(a0)
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SREG s6, RISCV_CONTEXT_S6(a0)
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SREG s7, RISCV_CONTEXT_S7(a0)
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SREG s8, RISCV_CONTEXT_S8(a0)
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SREG s9, RISCV_CONTEXT_S9(a0)
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SREG s10, RISCV_CONTEXT_S10(a0)
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SREG s11, RISCV_CONTEXT_S11(a0)
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sw a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0)
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.Lrestore:
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lw a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a1)
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LREG ra, RISCV_CONTEXT_RA(a1)
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LREG sp, RISCV_CONTEXT_SP(a1)
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LREG tp, RISCV_CONTEXT_TP(a1)
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LREG s0, RISCV_CONTEXT_S0(a1)
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LREG s1, RISCV_CONTEXT_S1(a1)
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LREG s2, RISCV_CONTEXT_S2(a1)
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LREG s3, RISCV_CONTEXT_S3(a1)
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LREG s4, RISCV_CONTEXT_S4(a1)
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LREG s5, RISCV_CONTEXT_S5(a1)
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LREG s6, RISCV_CONTEXT_S6(a1)
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LREG s7, RISCV_CONTEXT_S7(a1)
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LREG s8, RISCV_CONTEXT_S8(a1)
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LREG s9, RISCV_CONTEXT_S9(a1)
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LREG s10, RISCV_CONTEXT_S10(a1)
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LREG s11, RISCV_CONTEXT_S11(a1)
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sw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
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ret
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SYM(_CPU_Context_restore):
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mv a1, a0
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GET_SELF_CPU_CONTROL a2
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j .Lrestore
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/* TODO no FP support for riscv32 yet */
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SYM(_CPU_Context_restore_fp):
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nop
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SYM(_CPU_Context_save_fp):
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nop
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