forked from Imagelibrary/rtems
6597e5839f
* startup/bspstart.c: Added dummy implementation of firmware syscalls for use with QEMU. Dummy handler is installed if no pre-existing firmware handler is found.
749 lines
23 KiB
C
749 lines
23 KiB
C
/*
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* BSP startup
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*
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* This routine starts the application. It includes application,
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* board, and monitor specific initialization and configuration.
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* The generic CPU dependent initialization has been performed
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* before this routine is invoked.
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*
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* Author: W. Eric Norum <norume@aps.anl.gov>
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*
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* COPYRIGHT (c) 2005.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <bsp.h>
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#include <rtems/libio.h>
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#include <rtems/error.h>
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#include <rtems/libcsupport.h>
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#include <stdio.h>
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#include <string.h>
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#include <errno.h>
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/*
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* Location of 'VME' access
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*/
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#define VME_ONE_BASE 0x30000000
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#define VME_TWO_BASE 0x31000000
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/*
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* CPU-space access
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* The NOP after writing the CACR is there to address the following issue as
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* described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
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*
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* 6 Possible Cache Corruption after Setting CACR[CINV]
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* 6.1 Description
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* The cache on the MCF5282 was enhanced to function as a unified data and
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* instruction cache, an instruction cache, or an operand cache. The cache
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* function and organization is controlled by the cache control register (CACR).
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* The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
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* If the cache is configured as a unified cache and the CINV bit is set, the
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* scope of the cache clear is controlled by two other bits in the CACR,
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* INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
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* cache only). These bits allow the entire cache, just the instruction
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* portion of the cache, or just the data portion of the cache to be cleared.
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* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
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* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
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* then cache corruption may occur.
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*
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* 6.2 Workaround
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* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
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* should be followed immediately by a NOP instruction. This avoids the cache
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* corruption problem.
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* DATECODES AFFECTED: All
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*
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*
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* Buffered writes must be disabled as described in "MCF5282 Chip Errata",
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* MCF5282DE, Rev. 6, 5/2009:
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* SECF124: Buffered Write May Be Executed Twice
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* Errata type: Silicon
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* Affected component: Cache
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* Description: If buffered writes are enabled using the CACR or ACR
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* registers, the imprecise write transaction generated
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* by a buffered write may be executed twice.
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* Workaround: Do not enable buffered writes in the CACR or ACR registers:
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* CACR[8] = DBWE (default buffered write enable) must be 0
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* ACRn[5] = BUFW (buffered write enable) must be 0
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* Fix plan: Currently, there are no plans to fix this.
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*/
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#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
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#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
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#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
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#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
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/*
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* Read/write copy of cache registers
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* Split instruction/data or instruction-only
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* Allow CPUSHL to invalidate a cache line
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* Disable buffered writes
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* No burst transfers on non-cacheable accesses
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* Default cache mode is *disabled* (cache only ACRx areas)
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*/
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uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
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#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
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MCF5XXX_CACR_DISD |
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#endif
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MCF5XXX_CACR_DCM;
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uint32_t mcf5282_acr0_mode = 0;
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uint32_t mcf5282_acr1_mode = 0;
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/*
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* Cannot be frozen
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*/
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void _CPU_cache_freeze_data(void) {}
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void _CPU_cache_unfreeze_data(void) {}
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void _CPU_cache_freeze_instruction(void) {}
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void _CPU_cache_unfreeze_instruction(void) {}
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/*
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* Write-through data cache -- flushes are unnecessary
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*/
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void _CPU_cache_flush_1_data_line(const void *d_addr) {}
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void _CPU_cache_flush_entire_data(void) {}
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void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
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m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
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rtems_interrupt_enable(level);
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}
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void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI;
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m68k_set_cacr(mcf5282_cacr_mode);
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rtems_interrupt_enable(level);
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}
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void _CPU_cache_invalidate_entire_instruction(void)
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{
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m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
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}
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void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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/*
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* Top half of cache is I-space
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*/
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addr = (void *)((int)addr | 0x400);
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asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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}
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void _CPU_cache_enable_data(void)
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{
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#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD;
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m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
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rtems_interrupt_enable(level);
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#endif
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}
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void _CPU_cache_disable_data(void)
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{
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#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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mcf5282_cacr_mode |= MCF5XXX_CACR_DISD;
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m68k_set_cacr(mcf5282_cacr_mode);
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rtems_interrupt_enable(level);
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#endif
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}
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void _CPU_cache_invalidate_entire_data(void)
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{
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#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
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m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
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#endif
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}
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void _CPU_cache_invalidate_1_data_line(const void *addr)
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{
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#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
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/*
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* Bottom half of cache is D-space
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*/
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addr = (void *)((int)addr & ~0x400);
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asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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#endif
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}
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/*
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* Use the shared implementations of the following routines
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*/
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void bsp_libc_init( void *, uint32_t, int );
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void bsp_pretasking_hook(void); /* m68k version */
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extern void bsp_fake_syscall();
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/*
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* The Arcturus boot ROM prints exception information improperly
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* so use this default exception handler instead. This one also
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* prints a call backtrace
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*/
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static void handler(int pc)
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{
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int level;
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static volatile int reent;
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extern char _RamSize[];
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rtems_interrupt_disable(level);
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if (reent++) bsp_reset(0);
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{
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int *p = &pc;
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int info = p[-1];
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int pc = p[0];
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int format = (info >> 28) & 0xF;
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int faultStatus = ((info >> 24) & 0xC) | ((info >> 16) & 0x3);
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int vector = (info >> 18) & 0xFF;
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int statusRegister = info & 0xFFFF;
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int *fp;
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printk("\n\nPC:%x SR:%x VEC:%x FORMAT:%x STATUS:%x\n", pc,
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statusRegister,
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vector,
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format,
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faultStatus);
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fp = &p[-2];
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for(;;) {
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int *nfp = (int *)*fp;
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if ((nfp <= fp)
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|| ((char *)nfp >= _RamSize)
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|| ((char *)(nfp[1]) >= _RamSize))
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break;
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printk("FP:%x -> %x PC:%x\n", fp, nfp, nfp[1]);
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fp = nfp;
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}
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}
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rtems_task_suspend(0);
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rtems_panic("done");
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}
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/*
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* bsp_start
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*
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* This routine does the bulk of the system initialisation.
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*/
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void bsp_start( void )
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{
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int i;
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extern char _WorkspaceBase[];
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extern char _RamBase[], _RamSize[];
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extern unsigned long _M68k_Ramsize;
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_M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */
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/*
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* Allocate the memory for the RTEMS Work Space. This can come from
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* a variety of places: hard coded address, malloc'ed from outside
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* RTEMS world (e.g. simulator or primitive memory manager), or (as
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* typically done by stock BSPs) by subtracting the required amount
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* of work space from the last physical address on the CPU board.
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*/
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/*
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* Set up default exception handler
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*/
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for (i = 2 ; i < 256 ; i++)
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if (i != (32+2)) /* Catch all but bootrom system calls */
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*((void (**)(int))(i * 4)) = handler;
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/*
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* Qemu has no trap handler; install our fake syscall
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* implementation if there is no existing handler.
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*/
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if ( 0 == *((void (**)(int))((32+2) * 4)) )
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*((void (**)(int))((32+2) * 4)) = bsp_fake_syscall;
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/*
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* Need to "allocate" the memory for the RTEMS Workspace and
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* tell the RTEMS configuration where it is. This memory is
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* not malloc'ed. It is just "pulled from the air".
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*/
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Configuration.work_space_start = (void *)_WorkspaceBase;
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/*
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* Invalidate the cache and disable it
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*/
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m68k_set_acr0(mcf5282_acr0_mode);
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m68k_set_acr1(mcf5282_acr1_mode);
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m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
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/*
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* Cache SDRAM
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* Enable buffered writes
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* As Device Errata SECF124 notes this may cause double writes,
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* but that's not really a big problem and benchmarking tests have
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* shown that buffered writes do gain some performance.
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*/
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mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase) |
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MCF5XXX_ACR_AM((uint32_t)_RamSize-1) |
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MCF5XXX_ACR_EN |
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MCF5XXX_ACR_SM_IGNORE |
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MCF5XXX_ACR_BWE;
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m68k_set_acr0(mcf5282_acr0_mode);
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/*
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* Enable the cache
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*/
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m68k_set_cacr(mcf5282_cacr_mode);
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/*
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* Set up CS* space (fake 'VME')
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* Two A24/D16 spaces, supervisor data acces
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*/
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MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
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MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
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MCF5282_CS_CSMR_CI |
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MCF5282_CS_CSMR_SC |
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MCF5282_CS_CSMR_UC |
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MCF5282_CS_CSMR_UD |
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MCF5282_CS_CSMR_V;
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MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
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MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
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MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
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MCF5282_CS_CSMR_CI |
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MCF5282_CS_CSMR_SC |
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MCF5282_CS_CSMR_UC |
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MCF5282_CS_CSMR_UD |
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MCF5282_CS_CSMR_V;
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MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
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MCF5282_GPIO_PJPAR |= 0x06;
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}
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uint32_t bsp_get_CPU_clock_speed(void)
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{
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extern char _CPUClockSpeed[];
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return( (uint32_t)_CPUClockSpeed);
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}
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/*
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* Interrupt controller allocation
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*/
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rtems_status_code
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bsp_allocate_interrupt(int level, int priority)
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{
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static char used[7];
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rtems_interrupt_level l;
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rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
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if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
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return RTEMS_INVALID_NUMBER;
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rtems_interrupt_disable(l);
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if ((used[level-1] & (1 << priority)) == 0) {
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used[level-1] |= (1 << priority);
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ret = RTEMS_SUCCESSFUL;
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}
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rtems_interrupt_enable(l);
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return ret;
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}
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/*
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* Arcturus bootloader system calls
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*/
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#define syscall_return(type, ret) \
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do { \
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if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
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errno = -(ret); \
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ret = -1; \
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} \
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return (type)(ret); \
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} while (0)
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#define syscall_1(type,name,d1type,d1) \
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type bsp_##name(d1type d1) \
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{ \
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long ret; \
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register long __d1 __asm__ ("%d1") = (long)d1; \
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__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
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"trap #2\n\t" \
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"move.l %%d0,%0" \
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: "=g" (ret) \
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: "i" (SysCode_##name), "d" (__d1) \
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: "d0" ); \
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syscall_return(type,ret); \
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}
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#define syscall_2(type,name,d1type,d1,d2type,d2) \
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type bsp_##name(d1type d1, d2type d2) \
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{ \
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long ret; \
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register long __d1 __asm__ ("%d1") = (long)d1; \
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register long __d2 __asm__ ("%d2") = (long)d2; \
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__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
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"trap #2\n\t" \
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"move.l %%d0,%0" \
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: "=g" (ret) \
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: "i" (SysCode_##name), "d" (__d1),\
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"d" (__d2) \
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: "d0" ); \
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syscall_return(type,ret); \
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}
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#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \
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type bsp_##name(d1type d1, d2type d2, d3type d3) \
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{ \
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long ret; \
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register long __d1 __asm__ ("%d1") = (long)d1; \
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register long __d2 __asm__ ("%d2") = (long)d2; \
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register long __d3 __asm__ ("%d3") = (long)d3; \
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__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
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"trap #2\n\t" \
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"move.l %%d0,%0" \
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: "=g" (ret) \
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: "i" (SysCode_##name), "d" (__d1),\
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"d" (__d2),\
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"d" (__d3) \
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: "d0" ); \
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syscall_return(type,ret); \
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}
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#define SysCode_reset 0 /* reset */
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#define SysCode_program 5 /* program flash memory */
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#define SysCode_gethwaddr 12 /* get hardware address */
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#define SysCode_getbenv 14 /* get bootloader environment variable */
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#define SysCode_setbenv 15 /* set bootloader environment variable */
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#define SysCode_flash_erase_range 19 /* erase a section of flash */
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#define SysCode_flash_write_range 20 /* write a section of flash */
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syscall_1(int, reset, int, flags)
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syscall_1(unsigned const char *, gethwaddr, int, a)
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syscall_1(const char *, getbenv, const char *, a)
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syscall_1(int, setbenv, const char *, a)
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syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
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syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
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syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
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/* Provide a dummy-implementation of these syscalls
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* for qemu (which lacks the firmware).
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*/
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#define __STR(x) #x
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#define __STRSTR(x) __STR(x)
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#define ERRVAL __STRSTR(EACCES)
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/* reset-control register */
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#define RCR "__IPSBAR + 0x110000"
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asm(
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"bsp_fake_syscall: \n"
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" cmpl #0, %d0 \n" /* sysreset */
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" bne 1f \n"
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" moveb #0x80, %d0 \n"
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" moveb %d0, "RCR" \n" /* reset-controller */
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/* should never get here - but we'd return -EACCESS if we do */
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"1: \n"
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" cmpl #12, %d0 \n" /* gethwaddr */
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" beq 2f \n"
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" cmpl #14, %d0 \n" /* getbenv */
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" beq 2f \n"
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" movel #-"ERRVAL", %d0 \n" /* return -EACCESS */
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" rte \n"
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"2: \n"
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" movel #0, %d0 \n" /* return NULL */
|
|
" rte \n"
|
|
);
|
|
|
|
|
|
/*
|
|
* 'Extended BSP' routines
|
|
* Should move to cpukit/score/cpu/m68k/cpu.c someday.
|
|
*/
|
|
|
|
rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
|
|
int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
|
|
int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
|
|
|
|
/*
|
|
* 'VME' interrupt support
|
|
* Interrupt vectors 192-255 are set aside for use by external logic which
|
|
* drives IRQ1*. The actual interrupt source is read from the external
|
|
* logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant
|
|
* byte read from this location is set as long as the external logic has
|
|
* interrupts to be serviced. The least-significant six bits indicate the
|
|
* interrupt source within the external logic and are used to select the
|
|
* specified interupt handler.
|
|
*/
|
|
#define NVECTOR 256
|
|
#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
|
|
#define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe))
|
|
|
|
static struct handlerTab {
|
|
BSP_VME_ISR_t func;
|
|
void *arg;
|
|
} handlerTab[NVECTOR];
|
|
|
|
BSP_VME_ISR_t
|
|
BSP_getVME_isr(unsigned long vector, void **pusrArg)
|
|
{
|
|
if (vector >= NVECTOR)
|
|
return (BSP_VME_ISR_t)NULL;
|
|
if (pusrArg)
|
|
*pusrArg = handlerTab[vector].arg;
|
|
return handlerTab[vector].func;
|
|
}
|
|
|
|
static rtems_isr
|
|
fpga_trampoline (rtems_vector_number v)
|
|
{
|
|
/*
|
|
* Handle FPGA interrupts until all have been consumed
|
|
*/
|
|
int loopcount = 0;
|
|
while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
|
|
v = 192 + (v & 0x3f);
|
|
if (++loopcount >= 50) {
|
|
rtems_interrupt_level level;
|
|
rtems_interrupt_disable(level);
|
|
printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f);
|
|
MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
|
|
rtems_interrupt_enable(level);
|
|
return;
|
|
}
|
|
if (handlerTab[v].func) {
|
|
(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
|
|
}
|
|
else {
|
|
rtems_interrupt_level level;
|
|
rtems_vector_number nv;
|
|
rtems_interrupt_disable(level);
|
|
printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f);
|
|
if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0)
|
|
&& ((nv & 0x3f) == (v & 0x3f))) {
|
|
printk("DISABLING ALL FPGA INTERRUPTS.\n");
|
|
MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
|
|
}
|
|
rtems_interrupt_enable(level);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static rtems_isr
|
|
trampoline (rtems_vector_number v)
|
|
{
|
|
if (handlerTab[v].func)
|
|
(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
|
|
}
|
|
|
|
static void
|
|
enable_irq(unsigned source)
|
|
{
|
|
rtems_interrupt_level level;
|
|
rtems_interrupt_disable(level);
|
|
if (source >= 32)
|
|
MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
|
|
else
|
|
MCF5282_INTC0_IMRL &= ~((1 << source) |
|
|
MCF5282_INTC_IMRL_MASKALL);
|
|
rtems_interrupt_enable(level);
|
|
}
|
|
|
|
static void
|
|
disable_irq(unsigned source)
|
|
{
|
|
rtems_interrupt_level level;
|
|
|
|
rtems_interrupt_disable(level);
|
|
if (source >= 32)
|
|
MCF5282_INTC0_IMRH |= (1 << (source - 32));
|
|
else
|
|
MCF5282_INTC0_IMRL |= (1 << source);
|
|
rtems_interrupt_enable(level);
|
|
}
|
|
|
|
void
|
|
BSP_enable_irq_at_pic(rtems_vector_number v)
|
|
{
|
|
int source = v - 64;
|
|
|
|
if ( source > 0 && source < 64 ) {
|
|
enable_irq(source);
|
|
}
|
|
}
|
|
|
|
void
|
|
BSP_disable_irq_at_pic(rtems_vector_number v)
|
|
{
|
|
int source = v - 64;
|
|
|
|
if ( source > 0 && source < 64 ) {
|
|
disable_irq(source);
|
|
}
|
|
}
|
|
|
|
int
|
|
BSP_irq_is_enabled_at_pic(rtems_vector_number v)
|
|
{
|
|
int source = v - 64;
|
|
|
|
if ( source > 0 && source < 64 ) {
|
|
return ! ((source >= 32) ?
|
|
MCF5282_INTC0_IMRH & (1 << (source - 32)) :
|
|
MCF5282_INTC0_IMRL & (1 << source));
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
|
|
static int
|
|
init_intc0_bit(unsigned long vector)
|
|
{
|
|
rtems_interrupt_level level;
|
|
|
|
/*
|
|
* Find an unused level/priority if this is an on-chip (INTC0)
|
|
* source and this is the first time the source is being used.
|
|
* Interrupt sources 1 through 7 are fixed level/priority
|
|
*/
|
|
|
|
if ((vector >= 65) && (vector <= 127)) {
|
|
int l, p;
|
|
int source = vector - 64;
|
|
static unsigned char installed[8];
|
|
|
|
rtems_interrupt_disable(level);
|
|
if (installed[source/8] & (1 << (source % 8))) {
|
|
rtems_interrupt_enable(level);
|
|
return 0;
|
|
}
|
|
installed[source/8] |= (1 << (source % 8));
|
|
rtems_interrupt_enable(level);
|
|
for (l = 1 ; l < 7 ; l++) {
|
|
for (p = 0 ; p < 8 ; p++) {
|
|
if ((source < 8)
|
|
|| (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
|
|
if (source < 8)
|
|
MCF5282_EPORT_EPIER |= 1 << source;
|
|
else
|
|
*(&MCF5282_INTC0_ICR1 + (source - 1)) =
|
|
MCF5282_INTC_ICR_IL(l) |
|
|
MCF5282_INTC_ICR_IP(p);
|
|
enable_irq(source);
|
|
return 0;
|
|
}
|
|
}
|
|
}
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
|
|
{
|
|
rtems_isr_entry old_handler;
|
|
rtems_interrupt_level level;
|
|
|
|
/*
|
|
* Register the handler information
|
|
*/
|
|
if (vector >= NVECTOR)
|
|
return -1;
|
|
handlerTab[vector].func = handler;
|
|
handlerTab[vector].arg = usrArg;
|
|
|
|
/*
|
|
* If this is an external FPGA ('VME') vector set up the real IRQ.
|
|
*/
|
|
if ((vector >= 192) && (vector <= 255)) {
|
|
int i;
|
|
static volatile int setupDone;
|
|
rtems_interrupt_disable(level);
|
|
if (setupDone) {
|
|
rtems_interrupt_enable(level);
|
|
return 0;
|
|
}
|
|
setupDone = 1;
|
|
rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler);
|
|
i = init_intc0_bit(FPGA_VECTOR);
|
|
rtems_interrupt_enable(level);
|
|
return i;
|
|
}
|
|
|
|
/*
|
|
* Make the connection between the interrupt and the local handler
|
|
*/
|
|
rtems_interrupt_catch(trampoline, vector, &old_handler);
|
|
|
|
return init_intc0_bit(vector);
|
|
}
|
|
|
|
int
|
|
BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
|
|
{
|
|
if (vector >= NVECTOR)
|
|
return -1;
|
|
if ((handlerTab[vector].func != handler)
|
|
|| (handlerTab[vector].arg != usrArg))
|
|
return -1;
|
|
handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
|
|
{
|
|
unsigned long offset;
|
|
|
|
switch (am) {
|
|
default: return -1;
|
|
case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
|
|
case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
|
|
case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
|
|
}
|
|
*plocaladdr = vmeaddr + offset;
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
rtems_bsp_reset_cause(char *buf, size_t capacity)
|
|
{
|
|
int bit, rsr;
|
|
size_t i;
|
|
const char *cp;
|
|
|
|
if (buf == NULL)
|
|
return;
|
|
if (capacity)
|
|
buf[0] = '\0';
|
|
rsr = MCF5282_RESET_RSR;
|
|
for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) {
|
|
if (rsr & bit) {
|
|
switch (bit) {
|
|
case MCF5282_RESET_RSR_LVD: cp = "Low voltage"; break;
|
|
case MCF5282_RESET_RSR_SOFT: cp = "Software reset"; break;
|
|
case MCF5282_RESET_RSR_WDR: cp = "Watchdog reset"; break;
|
|
case MCF5282_RESET_RSR_POR: cp = "Power-on reset"; break;
|
|
case MCF5282_RESET_RSR_EXT: cp = "External reset"; break;
|
|
case MCF5282_RESET_RSR_LOC: cp = "Loss of clock"; break;
|
|
case MCF5282_RESET_RSR_LOL: cp = "Loss of lock"; break;
|
|
default: cp = "??"; break;
|
|
}
|
|
i += snprintf(buf+i, capacity-i, cp);
|
|
if (i >= capacity)
|
|
break;
|
|
rsr &= ~bit;
|
|
if (rsr == 0)
|
|
break;
|
|
i += snprintf(buf+i, capacity-i, ", ");
|
|
if (i >= capacity)
|
|
break;
|
|
}
|
|
}
|
|
}
|