forked from Imagelibrary/rtems
211 lines
7.0 KiB
C
211 lines
7.0 KiB
C
/******************************************************************************
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* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xttcps_hw.h
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* @addtogroup ttcps_v3_15
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* @{
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*
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* This file defines the hardware interface to one of the three timer counters
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* in the Ps block.
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*
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- -------------------------------------------------
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* 1.00a drg/jz 01/21/10 First release
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* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
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* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
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* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
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* mask 16 bit values for zynq and 32 bit values for
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* zynq ultrascale+mpsoc "
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* </pre>
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*
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******************************************************************************/
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#ifndef XTTCPS_HW_H /* prevent circular inclusions */
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#define XTTCPS_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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#ifdef __rtems__
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#include <xil_system.h>
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#endif
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/************************** Constant Definitions *****************************/
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/*
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* Flag for a9 processor
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*/
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#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
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#define ARMA9
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#endif
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/** @name Register Map
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*
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* Register offsets from the base address of the device.
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*
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* @{
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*/
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
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#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
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#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
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#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
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#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
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#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
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#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
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#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
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/* @} */
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/** @name Clock Control Register
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* Clock Control Register definitions
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* @{
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*/
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#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
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#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
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#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
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#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
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#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
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#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
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/* @} */
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/** @name Counter Control Register
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* Counter Control Register definitions
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* @{
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*/
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#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
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#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
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#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
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#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
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#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
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#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
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#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
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#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
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/* @} */
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/** @name Current Counter Value Register
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* Current Counter Value Register definitions
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* @{
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*/
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#if defined(ARMA9)
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#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
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#else
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#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */
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#endif
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/* @} */
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/** @name Interval Value Register
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* Interval Value Register is the maximum value the counter will count up or
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* down to.
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* @{
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*/
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#if defined(ARMA9)
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#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
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#else
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#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/
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#endif
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/* @} */
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/** @name Match Registers
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* Definitions for Match registers, each timer counter has three match
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* registers.
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* @{
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*/
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#if defined(ARMA9)
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#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
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#else
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#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */
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#endif
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#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
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/* @} */
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/** @name Interrupt Registers
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* Following register bit mask is for all interrupt registers.
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*
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* @{
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*/
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#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
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#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
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#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
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#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
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#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
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#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
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/* @} */
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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/**
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*
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* Read the given Timer Counter register.
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*
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* @param BaseAddress is the base address of the timer counter device.
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* @param RegOffset is the register offset to be read
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*
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* @return The 32-bit value of the register
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*
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* @note C-style signature:
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* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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*****************************************************************************/
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#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
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(Xil_In32((BaseAddress) + (u32)(RegOffset)))
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/****************************************************************************/
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/**
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*
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* Write the given Timer Counter register.
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*
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* @param BaseAddress is the base address of the timer counter device.
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* @param RegOffset is the register offset to be written
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* @param Data is the 32-bit value to write to the register
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*
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* @return None.
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*
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* @note C-style signature:
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* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
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* u32 Data)
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*
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*****************************************************************************/
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#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
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(Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
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/****************************************************************************/
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/**
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*
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* Calculate a match register offset using the Match Register index.
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*
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* @param MatchIndex is the 0-2 value of the match register
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*
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* @return MATCH_N_OFFSET.
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*
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* @note C-style signature:
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* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
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*
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*****************************************************************************/
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#define XTtcPs_Match_N_Offset(MatchIndex) \
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((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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/** @} */
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