forked from Imagelibrary/rtems
62c3d857b4
* include/bsp.h, pci/pci.c, startup/bspstart.c: Make PCI initialize function part of the unified PCI API as pci_initialize().
343 lines
7.5 KiB
C
343 lines
7.5 KiB
C
/*
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* COPYRIGHT (c) 1998 by Radstone Technology
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*
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*
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* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
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* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
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* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
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*
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* You are hereby granted permission to use, copy, modify, and distribute
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* this file, provided that this notice, plus the above copyright notice
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* and disclaimer, appears in all copies. Radstone Technology will provide
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* no support for this code.
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*
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*/
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#include <bsp.h>
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#include <pci.h>
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/* SCE 97/4/9
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*
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* Use PCI configuration space access mechanism 1
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*
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* This is the preferred access mechanism and must be used when accessing
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* bridged PCI busses.
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*
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* The address to be written to the PCI_CONFIG_ADDRESS port is constructed
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* thus (the representation below is little endian):
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*
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* 31 30 24 23 16 15 11 10 8 7 2 1 0
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* ----------------------------------------------------------------------
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* | 1 | Resvd | Bus Number | Dev Number | Fn Number | Reg Number | 0 | 0 |
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* ----------------------------------------------------------------------
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*
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* On bus 0, the first 'real' device is at Device number 11, the Eagle being
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* device 0. On all other busses, device numbering starts at 0.
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*/
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/*
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* Normal PCI device numbering on busses other than 0 is such that
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* that the first device (0) is attached to AD16, second (1) to AD17 etc.
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*/
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#define CONFIG_ADDRESS(Bus, Device, Function, Offset) \
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(0x80000000 | (Bus<<16) | \
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((Device+(((Bus==0)&&(Device>0)) ? 10 : 0))<<11) | \
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(Function<<8) | \
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(Offset&~0x03))
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#define BYTE_LANE_OFFSET(Offset) ((Offset)&0x3)
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/*
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* Private data
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*/
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static uint8_t ucMaxPCIBus;
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/*
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* Public routines
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*/
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rtems_status_code PCIConfigWrite8(
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uint8_t ucBusNumber,
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uint8_t ucSlotNumber,
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uint8_t ucFunctionNumber,
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uint8_t ucOffset,
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uint8_t ucValue
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)
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{
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ISR_Level Irql;
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/*
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* Ensure that accesses to the addr/data ports are indivisible
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*/
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_ISR_Disable(Irql);
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/*
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* Write to the configuration space address register
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*/
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outport_32(PCI_CONFIG_ADDR,
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CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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ucFunctionNumber, ucOffset));
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/*
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* Write to the configuration space data register with the appropriate
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* offset
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*/
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outport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), ucValue);
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_ISR_Enable(Irql);
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return(RTEMS_SUCCESSFUL);
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}
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rtems_status_code PCIConfigWrite16(
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uint8_t ucBusNumber,
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uint8_t ucSlotNumber,
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uint8_t ucFunctionNumber,
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uint8_t ucOffset,
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uint16_t usValue
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)
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{
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ISR_Level Irql;
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/*
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* Ensure that accesses to the addr/data ports are indivisible
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*/
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_ISR_Disable(Irql);
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/*
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* Write to the configuration space address register
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*/
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outport_32(PCI_CONFIG_ADDR,
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CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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ucFunctionNumber, ucOffset));
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/*
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* Write to the configuration space data register with the appropriate
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* offset
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*/
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outport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), usValue);
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_ISR_Enable(Irql);
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return(RTEMS_SUCCESSFUL);
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}
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rtems_status_code PCIConfigWrite32(
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uint8_t ucBusNumber,
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uint8_t ucSlotNumber,
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uint8_t ucFunctionNumber,
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uint8_t ucOffset,
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uint32_t ulValue
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)
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{
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ISR_Level Irql;
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/*
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* Ensure that accesses to the addr/data ports are indivisible
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*/
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_ISR_Disable(Irql);
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/*
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* Write to the configuration space address register
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*/
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outport_32(PCI_CONFIG_ADDR,
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CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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ucFunctionNumber, ucOffset));
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/*
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* Write to the configuration space data register with the appropriate
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* offset
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*/
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outport_32(PCI_CONFIG_DATA, ulValue);
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_ISR_Enable(Irql);
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return(RTEMS_SUCCESSFUL);
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}
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rtems_status_code PCIConfigRead8(
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uint8_t ucBusNumber,
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uint8_t ucSlotNumber,
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uint8_t ucFunctionNumber,
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uint8_t ucOffset,
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uint8_t *pucValue
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)
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{
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ISR_Level Irql;
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/*
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* Ensure that accesses to the addr/data ports are indivisible
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*/
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_ISR_Disable(Irql);
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/*
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* Write to the configuration space address register
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*/
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outport_32(PCI_CONFIG_ADDR,
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CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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ucFunctionNumber, ucOffset));
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/*
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* Read from the configuration space data register with the appropriate
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* offset
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*/
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inport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pucValue);
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_ISR_Enable(Irql);
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return(RTEMS_SUCCESSFUL);
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}
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rtems_status_code PCIConfigRead16(
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uint8_t ucBusNumber,
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uint8_t ucSlotNumber,
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uint8_t ucFunctionNumber,
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uint8_t ucOffset,
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uint16_t *pusValue
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)
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{
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ISR_Level Irql;
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/*
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* Ensure that accesses to the addr/data ports are indivisible
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*/
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_ISR_Disable(Irql);
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/*
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* Write to the configuration space address register
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*/
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outport_32(PCI_CONFIG_ADDR,
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CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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ucFunctionNumber, ucOffset));
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/*
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* Read from the configuration space data register with the appropriate
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* offset
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*/
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inport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pusValue);
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_ISR_Enable(Irql);
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return(RTEMS_SUCCESSFUL);
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}
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rtems_status_code PCIConfigRead32(
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uint8_t ucBusNumber,
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uint8_t ucSlotNumber,
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uint8_t ucFunctionNumber,
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uint8_t ucOffset,
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uint32_t *pulValue
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)
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{
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ISR_Level Irql;
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/*
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* Ensure that accesses to the addr/data ports are indivisible
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*/
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_ISR_Disable(Irql);
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/*
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* Write to the configuration space address register
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*/
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outport_32(PCI_CONFIG_ADDR,
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CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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ucFunctionNumber, ucOffset));
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/*
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* Read from the configuration space data register with the appropriate
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* offset
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*/
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inport_32(PCI_CONFIG_DATA, *pulValue);
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_ISR_Enable(Irql);
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return(RTEMS_SUCCESSFUL);
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}
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/*
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* This routine determines the maximum bus number in the system
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*/
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void pci_initialize()
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{
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uint8_t ucSlotNumber, ucFnNumber, ucNumFuncs;
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uint8_t ucHeader;
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uint8_t ucBaseClass, ucSubClass, ucMaxSubordinate;
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uint32_t ulDeviceID;
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/*
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* Scan PCI bus 0 looking for PCI-PCI bridges
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*/
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for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++)
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{
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(void)PCIConfigRead32(0,
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ucSlotNumber,
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0,
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PCI_CONFIG_VENDOR_LOW,
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&ulDeviceID);
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if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
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{
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/*
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* This slot is empty
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*/
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continue;
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}
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(void)PCIConfigRead8(0,
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ucSlotNumber,
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0,
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PCI_CONFIG_HEADER_TYPE,
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&ucHeader);
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if(ucHeader&PCI_MULTI_FUNCTION)
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{
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ucNumFuncs=PCI_MAX_FUNCTIONS;
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}
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else
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{
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ucNumFuncs=1;
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}
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for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++)
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{
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(void)PCIConfigRead32(0,
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ucSlotNumber,
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ucFnNumber,
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PCI_CONFIG_VENDOR_LOW,
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&ulDeviceID);
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if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
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{
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/*
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* This slot/function is empty
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*/
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continue;
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}
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/*
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* This slot/function has a device fitted.
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*/
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(void)PCIConfigRead8(0,
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ucSlotNumber,
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ucFnNumber,
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PCI_CONFIG_CLASS_CODE_U,
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&ucBaseClass);
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(void)PCIConfigRead8(0,
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ucSlotNumber,
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ucFnNumber,
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PCI_CONFIG_CLASS_CODE_M,
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&ucSubClass);
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if((ucBaseClass==PCI_BASE_CLASS_BRIDGE) &&
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(ucSubClass==PCI_SUB_CLASS_BRIDGE_PCI))
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{
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/*
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* We have found a PCI-PCI bridge
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*/
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(void)PCIConfigRead8(0,
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ucSlotNumber,
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ucFnNumber,
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PCI_BRIDGE_SUBORDINATE_BUS,
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&ucMaxSubordinate);
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if(ucMaxSubordinate>ucMaxPCIBus)
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{
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ucMaxPCIBus=ucMaxSubordinate;
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}
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}
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}
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}
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}
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/*
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* Return the number of PCI busses in the system
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*/
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uint8_t BusCountPCI()
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{
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return(ucMaxPCIBus+1);
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}
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