forked from Imagelibrary/rtems
110 lines
4.8 KiB
Perl
110 lines
4.8 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-1999.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@chapter Board Support Packages
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@section Introduction
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An RTEMS Board Support Package (BSP) must be designed to support a
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particular processor and target board combination. This chapter presents a
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discussion of i386 specific BSP issues. For more information on developing
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a BSP, refer to the chapter titled Board Support Packages in the RTEMS
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Applications User's Guide.
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@section System Reset
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An RTEMS based application is initiated when the i386
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processor is reset. When the i386 is reset,
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@itemize @bullet
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@item The EAX register is set to indicate the results of the processor's
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power-up self test. If the self-test was not executed, the contents of
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this register are undefined. Otherwise, a non-zero value indicates the
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processor is faulty and a zero value indicates a successful self-test.
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@item The DX register holds a component identifier and revision level. DH
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contains 3 to indicate an i386 component and DL contains a unique revision
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level indicator.
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@item Control register zero (CR0) is set such that the processor is in real
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mode with paging disabled. Other portions of CR0 are used to indicate the
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presence of a numeric coprocessor.
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@item All bits in the extended flags register (EFLAG) which are not
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permanently set are cleared. This inhibits all maskable interrupts.
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@item The Interrupt Descriptor Register (IDTR) is set to point at address
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zero.
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@item All segment registers are set to zero.
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@item The instruction pointer is set to 0x0000FFF0. The first instruction
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executed after a reset is actually at 0xFFFFFFF0 because the i386 asserts
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the upper twelve address until the first intersegment (FAR) JMP or CALL
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instruction. When a JMP or CALL is executed, the upper twelve address
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lines are lowered and the processor begins executing in the first megabyte
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of memory.
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@end itemize
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Typically, an intersegment JMP to the application's initialization code is
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placed at address 0xFFFFFFF0.
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@section Processor Initialization
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This initialization code is responsible for initializing all data
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structures required by the i386 in protected mode and for actually entering
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protected mode. The i386 must be placed in protected mode and the segment
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registers and associated selectors must be initialized before the
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initialize_executive directive is invoked.
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The initialization code is responsible for initializing the Global
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Descriptor Table such that the i386 is in the thirty-two bit flat memory
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model with paging disabled. In this mode, the i386 automatically converts
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every address from a logical to a physical address each time it is used.
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For more information on the memory model used by RTEMS, please refer to the
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Memory Model chapter in this document.
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Since the processor is in real mode upon reset, the processor must be
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switched to protected mode before RTEMS can execute. Before switching to
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protected mode, at least one descriptor table and two descriptors must be
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created. Descriptors are needed for a code segment and a data segment. (
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This will give you the flat memory model.) The stack can be placed in a
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normal read/write data segment, so no descriptor for the stack is needed.
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Before the GDT can be used, the base address and limit must be loaded into
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the GDTR register using an LGDT instruction.
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If the hardware allows an NMI to be generated, you need to create the IDT
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and a gate for the NMI interrupt handler. Before the IDT can be used, the
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base address and limit for the idt must be loaded into the IDTR register
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using an LIDT instruction.
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Protected mode is entered by setting thye PE bit in the CR0 register.
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Either a LMSW or MOV CR0 instruction may be used to set this bit. Because
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the processor overlaps the interpretation of several instructions, it is
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necessary to discard the instructions from the read-ahead cache. A JMP
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instruction immediately after the LMSW changes the flow and empties the
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processor if intructions which have been pre-fetched and/or decoded. At
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this point, the processor is in protected mode and begins to perform
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protected mode application initialization.
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If the application requires that the IDTR be some value besides zero, then
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it should set it to the required value at this point. All tasks share the
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same i386 IDTR value. Because interrupts are enabled automatically by
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RTEMS as part of the initialize_executive directive, the IDTR MUST be set
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properly before this directive is invoked to insure correct interrupt
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vectoring. If processor caching is to be utilized, then it should be
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enabled during the reset application initialization code. The reset code
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which is executed before the call to initialize_executive has the following
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requirements:
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For more information regarding the i386s data structures and their
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contents, refer to Intel's 386 Programmer's Reference Manual.
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