forked from Imagelibrary/rtems
524 lines
10 KiB
C
524 lines
10 KiB
C
/**
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* @file
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*
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* @ingroup powerpc_shared
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*
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* @brief General purpose assembler macros, linker command file support and
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* some inline functions for direct register access.
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*/
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/*
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* Copyright (c) 2008
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* Embedded Brains GmbH
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* Obere Lagerstr. 30
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* D-82178 Puchheim
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* Germany
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* rtems@embedded-brains.de
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*
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* access function for Device Control Registers inspired by "ppc405common.h"
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* from Michael Hamel ADInstruments May 2008
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*
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* The license and distribution terms for this file may be found in the file
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* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
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*/
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/**
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* @defgroup powerpc_shared Shared PowerPC Code
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*/
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#ifndef LIBCPU_POWERPC_UTILITY_H
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#define LIBCPU_POWERPC_UTILITY_H
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#include <rtems/powerpc/registers.h>
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#ifndef ASM
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#include <stdint.h>
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#include <rtems/bspIo.h>
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#include <rtems/system.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/cpuIdent.h>
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#define LINKER_SYMBOL( sym) extern char sym []
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/**
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* @brief Read one byte from @a src.
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*/
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static inline uint8_t ppc_read_byte( const volatile void *src)
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{
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uint8_t value;
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asm volatile (
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"lbz %0, 0(%1)"
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: "=r" (value)
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: "r" (src)
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);
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return value;
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}
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/**
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* @brief Read one half word from @a src.
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*/
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static inline uint16_t ppc_read_half_word( const volatile void *src)
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{
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uint16_t value;
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asm volatile (
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"lhz %0, 0(%1)"
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: "=r" (value)
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: "r" (src)
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);
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return value;
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}
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/**
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* @brief Read one word from @a src.
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*/
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static inline uint32_t ppc_read_word( const volatile void *src)
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{
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uint32_t value;
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asm volatile (
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"lwz %0, 0(%1)"
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: "=r" (value)
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: "r" (src)
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);
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return value;
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}
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/**
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* @brief Write one byte @a value to @a dest.
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*/
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static inline void ppc_write_byte( uint8_t value, volatile void *dest)
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{
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asm volatile (
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"stb %0, 0(%1)"
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:
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: "r" (value), "r" (dest)
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);
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}
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/**
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* @brief Write one half word @a value to @a dest.
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*/
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static inline void ppc_write_half_word( uint16_t value, volatile void *dest)
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{
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asm volatile (
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"sth %0, 0(%1)"
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:
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: "r" (value), "r" (dest)
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);
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}
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/**
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* @brief Write one word @a value to @a dest.
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*/
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static inline void ppc_write_word( uint32_t value, volatile void *dest)
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{
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asm volatile (
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"stw %0, 0(%1)" :
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: "r" (value), "r" (dest)
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);
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}
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static inline void *ppc_stack_pointer()
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{
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void *sp;
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asm volatile (
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"mr %0, 1"
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: "=r" (sp)
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);
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return sp;
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}
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static inline void ppc_set_stack_pointer( void *sp)
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{
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asm volatile (
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"mr 1, %0"
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:
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: "r" (sp)
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);
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}
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static inline void *ppc_link_register()
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{
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void *lr;
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asm volatile (
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"mflr %0"
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: "=r" (lr)
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);
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return lr;
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}
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static inline void ppc_set_link_register( void *lr)
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{
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asm volatile (
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"mtlr %0"
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:
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: "r" (lr)
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);
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}
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static inline uint32_t ppc_machine_state_register()
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{
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uint32_t msr;
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asm volatile (
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"mfmsr %0"
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: "=r" (msr)
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);
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return msr;
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}
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static inline void ppc_set_machine_state_register( uint32_t msr)
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{
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asm volatile (
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"mtmsr %0"
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:
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: "r" (msr)
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);
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}
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/**
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* @brief Enables external exceptions.
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*
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* You can use this function to enable the external exceptions and restore the
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* machine state with ppc_external_exceptions_disable() later.
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*/
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static inline uint32_t ppc_external_exceptions_enable()
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{
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uint32_t current_msr;
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uint32_t new_msr;
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RTEMS_COMPILER_MEMORY_BARRIER();
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asm volatile (
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"mfmsr %0;"
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"ori %1, %0, 0x8000;"
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"mtmsr %1"
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: "=r" (current_msr), "=r" (new_msr)
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);
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return current_msr;
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}
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/**
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* @brief Restores machine state.
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*
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* @see ppc_external_exceptions_enable()
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*/
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static inline void ppc_external_exceptions_disable( uint32_t msr)
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{
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ppc_set_machine_state_register( msr);
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RTEMS_COMPILER_MEMORY_BARRIER();
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}
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static inline uint32_t ppc_decrementer_register()
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{
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uint32_t dec;
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PPC_Get_decrementer( dec);
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return dec;
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}
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static inline void ppc_set_decrementer_register( uint32_t dec)
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{
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PPC_Set_decrementer( dec);
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}
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#define PPC_STRINGOF(x) #x
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/* Do not use the following macros. Use the inline functions instead. */
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#define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr) \
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uint32_t val; \
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asm volatile ( \
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"mfspr %0, " #spr \
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: "=r" (val) \
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); \
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return val;
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#define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( spr) \
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr)
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#define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \
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asm volatile ( \
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"mtspr " #spr ", %0" \
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: \
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: "r" (val) \
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);
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#define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( spr, val) \
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val)
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/*
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* PPC4xx have Device Control Registers...
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*/
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#define PPC_DEVICE_CONTROL_REGISTER(dcr) \
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({uint32_t val;asm volatile ("mfspr %0," PPC_STRINGOF(dcr) \
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: "=r" (val)); val;})
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#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr,val) \
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do { \
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asm volatile ("mtspr " PPC_STRINGOF(dcr)",%0" \
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:: "r" (val)); \
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} while (0)
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static inline uint32_t ppc_special_purpose_register_0()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0);
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}
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static inline void ppc_set_special_purpose_register_0( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0, val);
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}
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static inline uint32_t ppc_special_purpose_register_1()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1);
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}
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static inline void ppc_set_special_purpose_register_1( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1, val);
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}
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static inline uint32_t ppc_special_purpose_register_2()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2);
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}
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static inline void ppc_set_special_purpose_register_2( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2, val);
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}
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static inline uint32_t ppc_special_purpose_register_3()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3);
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}
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static inline void ppc_set_special_purpose_register_3( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3, val);
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}
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static inline uint32_t ppc_special_purpose_register_4()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4);
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}
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static inline void ppc_set_special_purpose_register_4( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4, val);
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}
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static inline uint32_t ppc_special_purpose_register_5()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5);
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}
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static inline void ppc_set_special_purpose_register_5( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5, val);
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}
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static inline uint32_t ppc_special_purpose_register_6()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6);
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}
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static inline void ppc_set_special_purpose_register_6( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6, val);
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}
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static inline uint32_t ppc_special_purpose_register_7()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7);
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}
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static inline void ppc_set_special_purpose_register_7( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7, val);
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}
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static inline uint32_t ppc_user_special_purpose_register_0()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0);
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}
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static inline void ppc_set_user_special_purpose_register_0( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0, val);
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}
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static inline uint32_t ppc_timer_control_register()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR);
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}
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static inline void ppc_set_timer_control_register( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR, val);
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}
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static inline uint32_t ppc_timer_status_register()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR);
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}
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static inline void ppc_set_timer_status_register( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR, val);
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}
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static inline uint32_t ppc_decrementer_auto_reload_register()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR);
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}
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static inline void ppc_set_decrementer_auto_reload_register( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR, val);
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}
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static inline uint32_t ppc_hardware_implementation_dependent_register_0()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0);
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}
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static inline void ppc_set_hardware_implementation_dependent_register_0( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0, val);
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}
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static inline uint32_t ppc_hardware_implementation_dependent_register_1()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1);
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}
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static inline void ppc_set_hardware_implementation_dependent_register_1( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1, val);
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}
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static inline uint32_t ppc_time_base()
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{
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uint32_t val;
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CPU_Get_timebase_low( val);
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return val;
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}
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static inline void ppc_set_time_base( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWL, val);
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}
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static inline uint32_t ppc_time_base_upper()
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{
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PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( TBRU);
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}
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static inline void ppc_set_time_base_upper( uint32_t val)
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{
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PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWU, val);
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}
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static inline uint64_t ppc_time_base_64()
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{
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return PPC_Get_timebase_register();
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}
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static inline void ppc_set_time_base_64( uint64_t val)
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{
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PPC_Set_timebase_register( val);
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}
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#else /* ASM */
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#include <rtems/asm.h>
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.macro LA reg, addr
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lis \reg, (\addr)@h
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ori \reg, \reg, (\addr)@l
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.endm
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.macro LWI reg, value
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lis \reg, (\value)@h
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ori \reg, \reg, (\value)@l
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.endm
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.macro LW reg, addr
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lis \reg, \addr@ha
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lwz \reg, \addr@l(\reg)
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.endm
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/*
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* Tests the bits in reg1 against the bits set in mask. A match is indicated
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* by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register
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* reg2 is used to load the mask.
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*/
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.macro TSTBITS reg1, reg2, mask
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LWI \reg2, \mask
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and \reg1, \reg1, \reg2
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cmplw \reg1, \reg2
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.endm
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.macro SETBITS reg1, reg2, mask
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LWI \reg2, \mask
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or \reg1, \reg1, \reg2
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.endm
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.macro CLRBITS reg1, reg2, mask
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LWI \reg2, \mask
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andc \reg1, \reg1, \reg2
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.endm
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.macro GLOBAL_FUNCTION name
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.global \name
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.type \name, @function
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\name:
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.endm
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/*
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* Disables all asynchronous exeptions (interrupts) which may cause a context
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* switch.
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*/
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.macro INTERRUPT_DISABLE level, mask
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mfmsr \level
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mfspr \mask, sprg0
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andc \mask, \level, \mask
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mtmsr \mask
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.endm
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/*
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* Restore previous machine state.
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*/
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.macro INTERRUPT_ENABLE level
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mtmsr \level
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.endm
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#define LINKER_SYMBOL( sym) .extern sym
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#endif /* ASM */
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#endif /* LIBCPU_POWERPC_UTILITY_H */
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