forked from Imagelibrary/rtems
eebcc5be64
* cpu_supplement/arm.t: Update. * cpu_supplement/preface.texi: Typo. * cpu_supplement/general.t: Expanded abbreviation.
103 lines
3.3 KiB
Perl
103 lines
3.3 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@ifinfo
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@end ifinfo
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@chapter ARM Specific Information
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This chapter discusses the
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@uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture}
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dependencies in this port of RTEMS. The ARM family has a wide variety of
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implementations by a wide range of vendors. Consequently, there are many, many
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CPU models within it. Currently the ARMv5 (and compatible) architecture
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version as defined in the @code{ARMv5 Architecture Reference Manual} is supported by RTEMS.
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@subheading Architecture Documents
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For information on the ARM architecture refer to the
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@uref{http://infocenter.arm.com,ARM Infocenter}.
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@section CPU Model Dependent Features
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This section presents the set of features which vary
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across ARM implementations and are of importance to RTEMS. The set of CPU
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model feature macros are defined in the file
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@file{cpukit/score/cpu/arm/rtems/score/arm.h} based upon the particular CPU
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model flags specified on the compilation command line.
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@subsection CPU Model Name
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The macro @code{CPU_MODEL_NAME} is a string which designates
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the architectural level of this CPU model. See in
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@file{cpukit/score/cpu/arm/rtems/score/arm.h} for the values.
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@subsection Count Leading Zeroes Instruction
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The ARMv5 and later has the count leading zeroes @code{clz} instruction which
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could be used to speed up the find first bit operation. The use of this
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instruction should significantly speed up the scheduling associated with a
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thread blocking. This is currently not used.
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@subsection Floating Point Unit
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A floating point unit is currently not supported.
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@section Calling Conventions
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Please refer to the
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@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf,Procedure Call Standard for the ARM Architecture}.
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@section Memory Model
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A flat 32-bit memory model is supported. The board support package must take
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care about the MMU if necessary.
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@section Interrupt Processing
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The ARMv5 (and compatible) architecture has seven exception types:
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@itemize @bullet
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@item Reset
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@item Undefined
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@item Software Interrupt (SWI)
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@item Prefetch Abort
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@item Data Abort
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@item Interrupt (IRQ)
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@item Fast Interrupt (FIQ)
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@end itemize
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Of these types only the IRQ has explicit operating system support. It is
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intentional that the FIQ is not supported by the operating system. Without
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operating system support for the FIQ it is not necessary to disable them during
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critical sections of the system.
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@subsection Interrupt Levels
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The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as
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on most RTEMS ports. It is a bit mapping that corresponds the enable bit
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postions in the Current Program Status Register (CPSR). There are only two
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levels: IRQ enabled and IRQ disabled.
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@subsection Interrupt Stack
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The board support package must initialize the interrupt stack. The memory for
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the stacks is usually reserved in the linker script.
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@section Default Fatal Error Processing
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The default fatal error handler for this architecture performs the
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following actions:
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@itemize @bullet
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@item disables operating system supported interrupts (IRQ),
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@item places the error code in @code{r0}, and
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@item executes an infinite loop to simulate a halt processor instruction.
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@end itemize
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