forked from Imagelibrary/rtems
cb4c90b227
PR 1781/bsps * bf52x/include: Added additional MMR. * bf52x/interrupt: The BF52X processors have a different System interrupt controller than present in the 53X range of processors. The 52X have 8 interrupt assignment registers. The implementation uses tables to increase predictability. * serial/uart.?: Added DMA based and interrupt based transfer support. The uart code used a single ISR for TX and RX and tried to identify and multiplex inside the ISR. In the new code the type of interrupt is identified by the central ISR dispatcher bf52x/interrupt or interrupt/. This simplifies the UART ISR.
# # $Id$ # This is the README file for libcpu. This directory contains reusable libraries which are CPU dependent but not target board dependent. For example, the PowerPC has an on CPU decrementer register which may be used by all PowerPC BSP's for the Clock and Timer Drivers. Other examples include the caching support for the m68k CPU models and MIPS CPU model exception vectoring routines. This level of support will make it easier for others developing embedded applications on a given CPU.