forked from Imagelibrary/rtems
106 lines
2.5 KiB
C
106 lines
2.5 KiB
C
/*
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* Opencore OR1K CPU Dependent Source
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*
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* COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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*/
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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#include <rtems/score/cpu.h>
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/* bsp_start_vector_table_begin is the start address of the vector table
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* containing addresses to ISR Handlers. It's defined at the BSP linkcmds
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* and may differ from one BSP to another.
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*/
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extern char bsp_start_vector_table_begin[];
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/**
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* @brief Performs processor dependent initialization.
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*/
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void _CPU_Initialize(void)
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{
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/* Do nothing */
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}
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/**
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* @brief Sets the hardware interrupt level by the level value.
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*
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* @param[in] level for or1k can only range over two values:
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* 0 (enable interrupts) and 1 (disable interrupts). In future
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* implementations if fast context switch is implemented, the level
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* can range from 0 to 15. @see OpenRISC architecture manual.
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*
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*/
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void _CPU_ISR_Set_level(uint32_t level)
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{
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uint32_t sr = 0;
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level = (level > 0)? 1 : 0;
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/* map level bit to or1k interrupt enable/disable bit in sr register */
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level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
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sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
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if (level == 0){ /* Enable all interrupts */
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sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
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} else{
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sr &= ~CPU_OR1K_SPR_SR_IEE;
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}
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_OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
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}
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uint32_t _CPU_ISR_Get_level( void )
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{
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uint32_t sr = 0;
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sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
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return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1;
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}
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void _CPU_ISR_install_raw_handler(
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uint32_t vector,
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CPU_ISR_raw_handler new_handler,
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CPU_ISR_raw_handler *old_handler
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)
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{
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CPU_ISR_raw_handler *table =
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(CPU_ISR_raw_handler *) bsp_start_vector_table_begin;
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CPU_ISR_raw_handler current_handler;
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ISR_Level level;
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_ISR_Local_disable( level );
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current_handler = table [vector];
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/* The current handler is now the old one */
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if (old_handler != NULL) {
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*old_handler = current_handler;
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}
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/* Write only if necessary to avoid writes to a maybe read-only memory */
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if (current_handler != new_handler) {
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table [vector] = new_handler;
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}
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_ISR_Local_enable( level );
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}
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void *_CPU_Thread_Idle_body( uintptr_t ignored )
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{
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do {
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_OR1K_CPU_Sleep();
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} while (1);
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}
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