forked from Imagelibrary/rtems
511dc4b2be
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
543 lines
12 KiB
ArmAsm
543 lines
12 KiB
ArmAsm
/**
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* @file
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*
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* @ingroup qoriq
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*
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* @brief BSP start.
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*/
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/*
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* Copyright (c) 2010, 2017 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/score/percpu.h>
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#include <bsp.h>
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#include <libcpu/powerpc-utility.h>
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#include <bsp/vectors.h>
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#if (QORIQ_INITIAL_MSR & MSR_FP) != 0
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#define INITIALIZE_FPU
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#endif
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#define FIRST_TLB 0
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#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
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#define INITIAL_MSR r14
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#define START_STACK r15
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#define SAVED_LINK_REGISTER r16
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#define FDT_REGISTER r17
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.globl _start
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#ifdef RTEMS_SMP
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#if QORIQ_THREAD_COUNT > 1
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.globl _start_thread
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#endif
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.globl _start_secondary_processor
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#endif
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.globl bsp_exc_vector_base
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.section ".bsp_start_text", "ax"
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_start:
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mr FDT_REGISTER, r3
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bl .Linitearly
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/* Get start stack */
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LA START_STACK, _Configuration_Interrupt_stack_area_begin
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LA r3, _Configuration_Interrupt_stack_size
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add START_STACK, START_STACK, r3
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bl .Linitmore
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/* Copy fast text */
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LA r3, bsp_section_fast_text_begin
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LA r4, bsp_section_fast_text_load_begin
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LA r5, bsp_section_fast_text_size
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bl .Lcopy
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LA r3, bsp_section_fast_text_begin
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LA r4, bsp_section_fast_text_size
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bl rtems_cache_flush_multiple_data_lines
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Copy read-only data */
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LA r3, bsp_section_rodata_begin
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LA r4, bsp_section_rodata_load_begin
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LA r5, bsp_section_rodata_size
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bl .Lcopy
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/* Copy FDT into read-only data */
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mr r3, FDT_REGISTER
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bl bsp_fdt_copy
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Flush read-only data */
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LA r3, bsp_section_rodata_begin
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LA r4, bsp_section_rodata_size
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bl rtems_cache_flush_multiple_data_lines
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Copy fast data */
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LA r3, bsp_section_fast_data_begin
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LA r4, bsp_section_fast_data_load_begin
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LA r5, bsp_section_fast_data_size
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bl .Lcopy
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/* Copy data */
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LA r3, bsp_section_data_begin
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LA r4, bsp_section_data_load_begin
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LA r5, bsp_section_data_size
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bl .Lcopy
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/* NULL pointer access protection (only core 0 has to do this) */
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mfspr r3, BOOKE_PIR
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cmpwi r3, 0
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bne .Lnull_area_setup_done
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LA r3, bsp_section_start_begin
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srawi r3, r3, 2
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mtctr r3
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li r3, -4
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LWI r4, 0x44000002
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.Lnull_area_setup_loop:
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stwu r4, 4(r3)
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bdnz .Lnull_area_setup_loop
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.Lnull_area_setup_done:
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li r3, 1
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bl .Linitmmu
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/* Clear SBSS */
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LA r3, bsp_section_sbss_begin
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LA r4, bsp_section_sbss_size
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bl bsp_start_zero
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Clear BSS */
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LA r3, bsp_section_bss_begin
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LA r4, bsp_section_bss_size
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bl bsp_start_zero
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#ifndef __powerpc64__
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/* Set up EABI and SYSV environment */
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bl __eabi
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#endif
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/* Clear command line */
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li r3, 0
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bl boot_card
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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.Lcopy:
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PPC_REG_CMP r3, r4
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beqlr
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b memcpy
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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.Linitearly:
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#ifdef __powerpc64__
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/* Enable 64-bit computation mode for exceptions */
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mfspr r0, BOOKE_EPCR
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oris r0, r0, BOOKE_EPCR_ICM >> 16
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mtspr BOOKE_EPCR, r0
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/* Enable 64-bit computation mode */
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mfmsr r0
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oris r0, r0, MSR_CM >> 16
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mtmsr r0
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isync
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#endif
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/* Disable decrementer */
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mfspr r0, BOOKE_TCR
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LWI r4, BOOKE_TCR_DIE
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andc r0, r0, r4
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mtspr BOOKE_TCR, r0
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#ifdef QORIQ_INITIAL_SPEFSCR
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/* SPEFSCR initialization */
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LWI r0, QORIQ_INITIAL_SPEFSCR
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mtspr FSL_EIS_SPEFSCR, r0
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#endif
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#ifdef QORIQ_INITIAL_BUCSR
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/* BUCSR initialization */
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LWI r0, QORIQ_INITIAL_BUCSR
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mtspr FSL_EIS_BUCSR, r0
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isync
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#endif
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#if defined(QORIQ_INITIAL_HID0) && !defined(QORIQ_IS_HYPERVISOR_GUEST)
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/* HID0 initialization */
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LWI r0, QORIQ_INITIAL_HID0
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mtspr HID0, r0
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#endif
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#ifdef __powerpc64__
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LA32 r2, .TOC.
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#else
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/* Invalidate TLS anchor */
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li r2, 0
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/* Set small-data anchor */
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LA r13, _SDA_BASE_
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#endif
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SET_SELF_CPU_CONTROL r4, r5
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blr
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.Linitmore:
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mflr SAVED_LINK_REGISTER
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/* Invalidate all TS1 MMU entries */
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li r3, 1
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bl qoriq_tlb1_invalidate_all_by_ts
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Add TS1 entry for the first 4GiB of RAM */
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li r3, SCRATCH_TLB
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li r4, FSL_EIS_MAS1_TS
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li r5, FSL_EIS_MAS2_M
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li r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX
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li r7, 0
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li r8, 0
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li r9, 11
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bl qoriq_tlb1_write
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* MSR initialization and use TS1 for address translation */
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LWI INITIAL_MSR, QORIQ_INITIAL_MSR
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ori r0, INITIAL_MSR, MSR_IS | MSR_DS
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#ifdef QORIQ_IS_HYPERVISOR_GUEST
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oris r0, r0, MSR_GS >> 16
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#endif
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mtmsr r0
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isync
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/*
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* Initialize start stack. The stacks are statically allocated and
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* properly aligned.
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*/
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subi r1, START_STACK, PPC_DEFAULT_CACHE_LINE_SIZE
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li r0, 0
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PPC_REG_STORE r0, 0(r1)
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#ifdef INITIALIZE_FPU
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bl .Linitfpu
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#endif
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mtlr SAVED_LINK_REGISTER
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blr
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.Linitmmu:
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mflr SAVED_LINK_REGISTER
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/* Configure MMU */
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li r4, FIRST_TLB
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li r5, SCRATCH_TLB
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bl qoriq_mmu_config
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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mtmsr INITIAL_MSR
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isync
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li r3, SCRATCH_TLB
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bl qoriq_tlb1_invalidate
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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mtlr SAVED_LINK_REGISTER
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blr
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#ifdef INITIALIZE_FPU
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/*
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* Write a value to the FPRs to initialize the hidden tag bits. See
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* also "Core Software Initialization Requirements" of the e500mc
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* reference manual for example.
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*/
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.Linitfpu:
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li r0, 0
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stw r0, 0(r1)
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stw r0, 4(r1)
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lfd f0, 0(r1)
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fmr f1, f0
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fmr f2, f0
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fmr f3, f0
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fmr f4, f0
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fmr f5, f0
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fmr f6, f0
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fmr f7, f0
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fmr f8, f0
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fmr f9, f0
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fmr f10, f0
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fmr f11, f0
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fmr f12, f0
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fmr f13, f0
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fmr f14, f0
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fmr f15, f0
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fmr f16, f0
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fmr f17, f0
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fmr f18, f0
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fmr f19, f0
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fmr f20, f0
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fmr f21, f0
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fmr f22, f0
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fmr f23, f0
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fmr f24, f0
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fmr f25, f0
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fmr f26, f0
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fmr f27, f0
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fmr f28, f0
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fmr f29, f0
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fmr f30, f0
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fmr f31, f0
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blr
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#endif
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#ifdef RTEMS_SMP
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#if QORIQ_THREAD_COUNT > 1
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_start_thread:
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/* Adjust PIR */
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mfspr r0, BOOKE_PIR
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srawi r0, r0, 2
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ori r0, r0, 1
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mtspr BOOKE_PIR, r0
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bl .Linitearly
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/* Initialize start stack */
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GET_SELF_CPU_CONTROL r3
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PPC_REG_LOAD r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
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subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
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clrrwi r1, r1, PPC_STACK_ALIGN_POWER
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li r0, 0
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PPC_REG_STORE r0, 0(r1)
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#ifdef INITIALIZE_FPU
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bl .Linitfpu
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#endif
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b qoriq_start_thread
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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_start_secondary_processor:
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bl .Linitearly
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/* Get start stack */
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mr START_STACK, r3
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bl .Linitmore
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li r3, 0
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bl .Linitmmu
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b bsp_start_on_secondary_processor
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif /* RTEMS_SMP */
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#ifdef __powerpc64__
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#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop; nop; nop; nop
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#else
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#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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/* Exception vector prologues area */
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.section ".bsp_start_text", "ax"
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.align 4
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bsp_exc_vector_base:
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/* Critical input */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 0
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b ppc_exc_fatal_critical
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Machine check */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 1
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b ppc_exc_fatal_machine_check
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Data storage */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 2
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Instruction storage */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 3
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* External input */
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PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
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PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
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li r3, 4
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b ppc_exc_interrupt
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Alignment */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 5
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Program */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 6
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#ifdef __PPC_CPU_E6500__
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/* Floating-point unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 7
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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/* System call */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 8
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#ifdef __PPC_CPU_E6500__
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/* APU unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 9
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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/* Decrementer */
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#ifdef QORIQ_IS_HYPERVISOR_GUEST
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PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
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PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
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li r3, 10
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b ppc_exc_interrupt
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#else
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 10
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b ppc_exc_fatal_normal
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|
#endif
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|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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|
/* Fixed-interval timer interrupt */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 11
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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|
/* Watchdog timer interrupt */
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|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 12
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b ppc_exc_fatal_critical
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Data TLB error */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 13
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Instruction TLB error */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 14
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Debug */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 15
|
|
b ppc_exc_fatal_debug
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* SPE APU unavailable or AltiVec unavailable */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 32
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* SPE floating-point data exception or AltiVec assist */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 33
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
#ifndef __PPC_CPU_E6500__
|
|
/* SPE floating-point round exception */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 34
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
#endif
|
|
/* Performance monitor */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 35
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
#ifdef __PPC_CPU_E6500__
|
|
/* Processor doorbell interrupt */
|
|
#if defined(QORIQ_IS_HYPERVISOR_GUEST) && defined(RTEMS_SMP)
|
|
PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
|
|
PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
|
|
li r3, 36
|
|
b ppc_exc_interrupt
|
|
#else
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 36
|
|
b ppc_exc_fatal_normal
|
|
#endif
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Processor doorbell critical interrupt */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 37
|
|
b ppc_exc_fatal_critical
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Guest processor doorbell */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 38
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Guest processor doorbell critical and machine check */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 39
|
|
b ppc_exc_fatal_critical
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Hypervisor system call */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 40
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Hypervisor privilege */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 41
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* LRAT error */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 42
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
#endif
|
|
|
|
/* Symbol provided for debugging and tracing */
|
|
bsp_exc_vector_end:
|