forked from Imagelibrary/rtems
132 lines
5.0 KiB
Perl
132 lines
5.0 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-1998.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@include ../common/timemac.texi
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@tex
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\global\advance \smallskipamount by -4pt
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@end tex
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@ifinfo
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@node i960CA Timing Data, i960CA Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
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@end ifinfo
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@chapter Timing Data
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@ifinfo
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@menu
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* i960CA Timing Data Introduction::
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* i960CA Timing Data Hardware Platform::
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* i960CA Timing Data Interrupt Latency::
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* i960CA Timing Data Context Switch::
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* i960CA Timing Data Directive Times::
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* i960CA Timing Data Task Manager::
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* i960CA Timing Data Interrupt Manager::
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* i960CA Timing Data Clock Manager::
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* i960CA Timing Data Timer Manager::
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* i960CA Timing Data Semaphore Manager::
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* i960CA Timing Data Message Manager::
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* i960CA Timing Data Event Manager::
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* i960CA Timing Data Signal Manager::
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* i960CA Timing Data Partition Manager::
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* i960CA Timing Data Region Manager::
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* i960CA Timing Data Dual-Ported Memory Manager::
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* i960CA Timing Data I/O Manager::
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* i960CA Timing Data Rate Monotonic Manager::
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@end menu
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@end ifinfo
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NOTE: The i960CA board used by the RTEMS Project to
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obtain i960CA times is currently broken. The information in
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this chapter was obtained using Release 3.2.1.
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@ifinfo
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@node i960CA Timing Data Introduction, i960CA Timing Data Hardware Platform, i960CA Timing Data, i960CA Timing Data
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@end ifinfo
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@section Introduction
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The timing data for the i960CA version of RTEMS is
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provided along with the target dependent aspects concerning the
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gathering of the timing data. The hardware platform used to
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gather the times is described to give the reader a better
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understanding of each directive time provided. Also, provided
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is a description of the interrupt latency and the context
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switch times as they pertain to the i960CA version of RTEMS.
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@ifinfo
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@node i960CA Timing Data Hardware Platform, i960CA Timing Data Interrupt Latency, i960CA Timing Data Introduction, i960CA Timing Data
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@end ifinfo
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@section Hardware Platform
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All times reported except for the maximum period
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interrupts are disabled by RTEMS were measured using a Cyclone
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Microsystems CVME961 board. The CVME961 is a 33 Mhz board with
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dynamic RAM which has two wait state dynamic memory (four CPU
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cycles) for read accesses and one wait state (two CPU cycles)
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for write accesses. The Z8536 on a SQUALL SQSIO4 mezzanine
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board was used to measure elapsed time with one-half microsecond
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resolution. All sources of hardware interrupts are disabled,
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although the interrupt level of the i960CA allows all interrupts.
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The maximum interrupt disable period was measured by
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summing the number of CPU cycles required by each assembly
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language instruction executed while interrupts were disabled.
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Zero wait state memory was assumed. The total CPU cycles
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executed with interrupts disabled, including the instructions to
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disable and enable interrupts, was divided by 33 to simulate a
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i960CA executing at 33 Mhz with zero wait states.
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@ifinfo
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@node i960CA Timing Data Interrupt Latency, i960CA Timing Data Context Switch, i960CA Timing Data Hardware Platform, i960CA Timing Data
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@end ifinfo
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@section Interrupt Latency
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The maximum period with interrupts disabled within
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RTEMS is less than
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RTEMS_MAXIMUM_DISABLE_PERIOD microseconds including the instructions
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which disable and re-enable interrupts. The time required for
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the i960CA to generate an interrupt using the sysctl
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instruction, vectoring to an interrupt handler, and for the
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RTEMS entry overhead before invoking the user's interrupt
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handler are a total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
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microseconds. These combine to yield
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a worst case interrupt latency of less than
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RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
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microseconds. [NOTE: The maximum period with interrupts
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disabled within RTEMS was last calculated for Release
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RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
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It should be noted again that the maximum period with
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interrupts disabled within RTEMS is hand-timed. The interrupt
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vector and entry overhead time was generated on the Cyclone
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CVME961 benchmark platform using the sysctl instruction as the
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interrupt source.
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@ifinfo
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@node i960CA Timing Data Context Switch, i960CA Timing Data Directive Times, i960CA Timing Data Interrupt Latency, i960CA Timing Data
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@end ifinfo
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@section Context Switch
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The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
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microseconds on the Cyclone CVME961 benchmark platform. This
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time represents the raw context switch time with no user
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extensions configured. Additional execution time is required
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when a TSWITCH user extension is configured. The use of the
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TSWITCH extension is application dependent. Thus, its execution
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time is not considered part of the base context switch time.
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The i960CA has no hardware floating point capability
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and floating point tasks are not supported.
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The following table summarizes the context switch
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times for the CVME961 benchmark platform:
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@include timetbl.texi
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@tex
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\global\advance \smallskipamount by 4pt
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@end tex
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