forked from Imagelibrary/rtems
4f0b287a4a
* rtems/score/cpu_asm.h: Enhanced to include register offsets. * Makefile.am: Install rtems/score/cpu_asm.h. * cpu.c: Significantly enhanced including the implementation of _CPU_ISR_Get_level. * cpu_asm.S: Improved behavior of context switch and interrupt dispatching. * rtems/score/arm.h: Improved the CPU model name determination. * rtems/score/cpu.h: Improved interrupt disable/enable functions.
244 lines
6.7 KiB
C
244 lines
6.7 KiB
C
/*
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* ARM CPU Dependent Source
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*
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*
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* COPYRIGHT (c) 2000 Canon Research Centre France SA.
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* Emmanuel Raguet, mailto:raguet@crf.canon.fr
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*
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* Copyright (c) 2002 Advent Networks, Inc
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* Jay Monkman <jmonkman@adventnetworks.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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*/
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#include <rtems/system.h>
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#include <rtems.h>
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#include <rtems/bspIo.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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#include <rtems/score/thread.h>
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#include <rtems/score/cpu.h>
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/* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* INPUT PARAMETERS:
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* cpu_table - CPU table to initialize
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* thread_dispatch - address of ISR disptaching routine (unused)
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*
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*/
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void _CPU_Initialize(
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rtems_cpu_table *cpu_table,
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void (*thread_dispatch) /* ignored on this CPU */
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)
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{
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_CPU_Table = *cpu_table;
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}
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/*
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*
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* _CPU_ISR_Get_level - returns the current interrupt level
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*/
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unsigned32 _CPU_ISR_Get_level( void )
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{
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unsigned32 reg;
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asm volatile ("mrs %0, cpsr \n" \
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"and %0, %0, #0xc0 \n" \
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: "=r" (reg));
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return reg;
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}
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/*
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* _CPU_ISR_install_vector
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*
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* This kernel routine installs the RTEMS handler for the
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* specified vector.
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*
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* Input parameters:
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* vector - interrupt vector number
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* new_handler - replacement ISR for this vector number
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* old_handler - pointer to store former ISR for this vector number
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*
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* FIXME: This vector scheme should be changed to allow FIQ to be
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* handled better. I'd like to be able to put VectorTable
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* elsewhere - JTM
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*
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*
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* Output parameters: NONE
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*
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*/
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void _CPU_ISR_install_vector(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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/* pointer on the redirection table in RAM */
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long *VectorTable = (long *)(MAX_EXCEPTIONS * 4);
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if (old_handler != NULL) {
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old_handler = *(proc_ptr *)(VectorTable + vector);
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}
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*(VectorTable + vector) = (long)new_handler ;
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}
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void _CPU_Context_Initialize(
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Context_Control *the_context,
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unsigned32 *stack_base,
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unsigned32 size,
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unsigned32 new_level,
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void *entry_point,
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boolean is_fp
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)
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{
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the_context->register_sp = ((unsigned32)(stack_base)) + (size) ;
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the_context->register_pc = (entry_point);
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the_context->register_cpsr = (new_level | 0x13);
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}
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/*PAGE
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*
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* _CPU_Install_interrupt_stack
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*/
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void _CPU_Install_interrupt_stack( void )
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{
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/* FIXME: do something here */
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#if 0
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extern unsigned long _fiq_stack;
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extern unsigned long _fiq_stack_size;
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extern unsigned long _irq_stack;
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extern unsigned long _irq_stack_size;
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extern unsigned long _abt_stack;
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extern unsigned long _abt_stack_size;
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unsigned long *ptr;
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int i;
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ptr = &_fiq_stack;
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for (i = 0; i < ((int)&_fiq_stack_size/4); i++) {
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ptr[i] = 0x13131313;
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}
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ptr = &_irq_stack;
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for (i = 0; i < ((int)&_irq_stack_size/4); i++) {
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ptr[i] = 0xf0f0f0f0;
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}
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ptr = &_abt_stack;
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for (i = 0; i < ((int)&_abt_stack_size/4); i++) {
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ptr[i] = 0x55555555;
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}
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#endif
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}
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/*PAGE
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*
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* _CPU_Thread_Idle_body
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*
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* NOTES:
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*
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* 1. This is the same as the regular CPU independent algorithm.
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*
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* 2. If you implement this using a "halt", "idle", or "shutdown"
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* instruction, then don't forget to put it in an infinite loop.
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*
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* 3. Be warned. Some processors with onboard DMA have been known
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* to stop the DMA if the CPU were put in IDLE mode. This might
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* also be a problem with other on-chip peripherals. So use this
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* hook with caution.
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*/
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void _CPU_Thread_Idle_body( void )
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{
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while(1); /* FIXME: finish this */
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/* insert your "halt" instruction here */ ;
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}
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void _defaultExcHandler (CPU_Exception_frame *ctx)
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{
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printk("\n\r");
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printk("----------------------------------------------------------\n\r");
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printk("Exception 0x%x caught at PC 0x%x by thread %d\n",
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ctx->register_pc, ctx->register_lr - 4,
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_Thread_Executing->Object.id);
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printk("----------------------------------------------------------\n\r");
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printk("Processor execution context at time of the fault was :\n\r");
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printk("----------------------------------------------------------\n\r");
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printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r",
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ctx->register_r0, ctx->register_r1,
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ctx->register_r2, ctx->register_r3);
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printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r",
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ctx->register_r4, ctx->register_r5,
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ctx->register_r6, ctx->register_r7);
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printk(" r8 = %8x r9 = %8x r10 = %8x\n\r",
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ctx->register_r8, ctx->register_r9, ctx->register_r10);
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printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r",
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ctx->register_fp, ctx->register_ip,
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ctx->register_sp, ctx->register_lr - 4);
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printk("----------------------------------------------------------\n\r");
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if (_ISR_Nest_level > 0) {
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/*
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* In this case we shall not delete the task interrupted as
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* it has nothing to do with the fault. We cannot return either
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* because the eip points to the faulty instruction so...
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*/
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printk("Exception while executing ISR!!!. System locked\n\r");
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while(1);
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}
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else {
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printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r");
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rtems_task_delete(_Thread_Executing->Object.id);
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}
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}
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cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
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extern void _Exception_Handler_Undef_Swi();
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extern void _Exception_Handler_Abort();
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/* FIXME: put comments here */
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void rtems_exception_init_mngt()
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{
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ISR_Level level;
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_CPU_ISR_Disable(level);
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_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
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_Exception_Handler_Undef_Swi,
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NULL);
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_CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
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_Exception_Handler_Undef_Swi,
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NULL);
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_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
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_Exception_Handler_Abort,
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NULL);
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_CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
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_Exception_Handler_Abort,
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NULL);
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_CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,
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_Exception_Handler_Abort,
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NULL);
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_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,
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_Exception_Handler_Abort,
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NULL);
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_CPU_ISR_Enable(level);
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}
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