forked from Imagelibrary/rtems
121 lines
3.5 KiB
C
121 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* COPYRIGHT (c) 1989-2008.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems.h>
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#include <mcf5235/mcf5235.h>
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#include "cache.h"
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/*
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* Default value for the cacr is set by the BSP
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*/
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extern uint32_t cacr_mode;
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/*
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* Cannot be frozen
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*/
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static void _CPU_cache_freeze_data(void) {}
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static void _CPU_cache_unfreeze_data(void) {}
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static void _CPU_cache_freeze_instruction(void) {}
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static void _CPU_cache_unfreeze_instruction(void) {}
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/*
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* Write-through data cache -- flushes are unnecessary
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*/
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static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
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static void _CPU_cache_flush_entire_data(void) {}
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static void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode &= ~MCF5XXX_CACR_DIDI;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode |= MCF5XXX_CACR_DIDI;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_invalidate_entire_instruction(void)
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{
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m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
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}
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static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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/*
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* Top half of cache is I-space
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*/
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addr = (void *)((int)addr | 0x400);
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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}
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static void _CPU_cache_enable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode &= ~MCF5XXX_CACR_DISD;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_disable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode |= MCF5XXX_CACR_DISD;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_invalidate_entire_data(void)
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{
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m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
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}
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static void _CPU_cache_invalidate_1_data_line(const void *addr)
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{
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/*
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* Bottom half of cache is D-space
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*/
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addr = (void *)((int)addr & ~0x400);
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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}
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#include "../../../shared/cache/cacheimpl.h"
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