forked from Imagelibrary/rtems
4b3756d7bf
* console/console-io.c, startup/exception.S: Correct license URL and/or fix mistake in copyright notice. Both of these mistakes appear to be from code submitted after these changes were made previously.
632 lines
15 KiB
ArmAsm
632 lines
15 KiB
ArmAsm
/* exception.S
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*
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* This file contains a customized MIPS exception handler.
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* It hooks into the exception handler present in the resident
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* PMON debug monitor.
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*
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* Author: Bruce Robinson
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*
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* This code was derived from cpu_asm.S with the following copyright:
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*
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* COPYRIGHT (c) 1996 by Transition Networks Inc.
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of Transition Networks not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* Transition Networks makes no representations about the suitability
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* of this software for any purpose.
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*
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* Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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/* @(#)exception.S 7/27/04 1.00 */
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#include <rtems/mips/iregdef.h>
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#include <rtems/mips/idtcpu.h>
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#define FRAME(name,frm_reg,offset,ret_reg) \
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.globl name; \
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.ent name; \
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name:; \
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.frame frm_reg,offset,ret_reg
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#define ENDFRAME(name) \
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.end name
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#if __mips == 3
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/* 64 bit register operations */
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#define NOP nop
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#define ADD dadd
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#define STREG sd
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#define LDREG ld
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#define ADDU addu
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#define ADDIU addiu
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#define STREGC1 sdc1
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#define LDREGC1 ldc1
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#define R_SZ 8
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#define F_SZ 8
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#define SZ_INT 8
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#define SZ_INT_POW2 3
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/* XXX if we don't always want 64 bit register ops, then another ifdef */
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#elif __mips == 1
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/* 32 bit register operations*/
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#define NOP nop
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#define ADD add
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#define STREG sw
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#define LDREG lw
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#define ADDU add
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#define ADDIU addi
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#define STREGC1 swc1
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#define LDREGC1 lwc1
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#define R_SZ 4
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#define F_SZ 4
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#define SZ_INT 4
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#define SZ_INT_POW2 2
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#else
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#error "mips assembly: what size registers do I deal with?"
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#endif
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#define ISR_VEC_SIZE 4
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#define EXCP_STACK_SIZE (NREGS*R_SZ)
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#ifdef __GNUC__
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#define EXTERN(x,size) .extern x,size
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#else
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#define EXTERN(x,size)
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#endif
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EXTERN(_ISR_Nest_level, 4)
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EXTERN(_Thread_Dispatch_disable_level,4)
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EXTERN(_Context_Switch_necessary,4)
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EXTERN(_ISR_Signals_to_thread_executing,4)
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.extern _Thread_Dispatch
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.extern _ISR_Vector_table
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/* void __ISR_Handler()
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*
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* This routine provides the RTEMS interrupt management.
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*
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*/
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#if 0
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void _ISR_Handler()
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{
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/*
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* This discussion ignores a lot of the ugly details in a real
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* implementation such as saving enough registers/state to be
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* able to do something real. Keep in mind that the goal is
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* to invoke a user's ISR handler which is written in C and
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* uses a certain set of registers.
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*
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* Also note that the exact order is to a large extent flexible.
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* Hardware will dictate a sequence for a certain subset of
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* _ISR_Handler while requirements for setting
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*/
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/*
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* At entry to "common" _ISR_Handler, the vector number must be
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* available. On some CPUs the hardware puts either the vector
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* number or the offset into the vector table for this ISR in a
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* known place. If the hardware does not give us this information,
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* then the assembly portion of RTEMS for this port will contain
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* a set of distinct interrupt entry points which somehow place
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* the vector number in a known place (which is safe if another
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* interrupt nests this one) and branches to _ISR_Handler.
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*
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*/
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#endif
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FRAME(rbtx4925_ISR_Handler,sp,0,ra)
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.set noreorder
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#if 0
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/* Activate TX4925 PIO19 signal for diagnostics */
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lui k0,0xff1f
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ori k0,k0,0xf500
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lw k0,(k0)
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lui k1,0x8
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or k1,k1,k0
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lui k0,0xff1f
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ori k0,k0,0xf500
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sw k1,(k0)
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#endif
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mfc0 k0,C0_CAUSE /* Determine if an interrupt generated this exception */
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nop
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and k1,k0,CAUSE_EXCMASK
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beq k1,zero,_chk_int /* If so, branch to service here */
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nop
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la k0,_int_esr_link /* Otherwise, jump to next exception handler in PMON exception chain */
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lw k0,(k0)
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lw k0,4(k0)
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j k0
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nop
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_chk_int:
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mfc0 k1,C0_SR
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nop
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and k0,k1
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and k0,(SR_IBIT1 | SR_IBIT2 | SR_IBIT3)
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beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */
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nop
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/* For debugging interrupts, clear EXL to allow breakpoints */
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#if 0
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MFC0 k0, C0_SR
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li k1,SR_EXL /* Clear EXL and Set IE to enable interrupts */
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not k1
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and k0,k1
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li k1,SR_IE
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or k0, k1
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mtc0 k0, C0_SR
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NOP
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#endif
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/*
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* save some or all context on stack
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* may need to save some special interrupt information for exit
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*/
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/* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */
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/* wastes a lot of stack space for context?? */
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ADDIU sp,sp,-EXCP_STACK_SIZE
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STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
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STREG v0, R_V0*R_SZ(sp)
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STREG v1, R_V1*R_SZ(sp)
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STREG a0, R_A0*R_SZ(sp)
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STREG a1, R_A1*R_SZ(sp)
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STREG a2, R_A2*R_SZ(sp)
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STREG a3, R_A3*R_SZ(sp)
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STREG t0, R_T0*R_SZ(sp)
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STREG t1, R_T1*R_SZ(sp)
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STREG t2, R_T2*R_SZ(sp)
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STREG t3, R_T3*R_SZ(sp)
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STREG t4, R_T4*R_SZ(sp)
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STREG t5, R_T5*R_SZ(sp)
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STREG t6, R_T6*R_SZ(sp)
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STREG t7, R_T7*R_SZ(sp)
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mflo t0
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STREG t8, R_T8*R_SZ(sp)
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STREG t0, R_MDLO*R_SZ(sp)
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STREG t9, R_T9*R_SZ(sp)
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mfhi t0
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STREG gp, R_GP*R_SZ(sp)
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STREG t0, R_MDHI*R_SZ(sp)
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STREG fp, R_FP*R_SZ(sp)
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.set noat
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STREG AT, R_AT*R_SZ(sp)
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.set at
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mfc0 t0,C0_SR
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dmfc0 t1,C0_EPC
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STREG t0,R_SR*R_SZ(sp)
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STREG t1,R_EPC*R_SZ(sp)
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/*
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*
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* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
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* if ( _ISR_Nest_level == 0 )
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* switch to software interrupt stack
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* #endif
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*/
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/*
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* _ISR_Nest_level++;
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*/
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lw t0,_ISR_Nest_level
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NOP
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add t0,t0,1
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sw t0,_ISR_Nest_level
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/*
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* _Thread_Dispatch_disable_level++;
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*/
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lw t1,_Thread_Dispatch_disable_level
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NOP
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add t1,t1,1
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sw t1,_Thread_Dispatch_disable_level
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/* DEBUG - Add the following code to disable interrupts and clear EXL in status register, this will
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allow memory exceptions to occur while servicing the current interrupt */
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#if 0
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li t0,~CAUSE_IP2_MASK /* Disable interrupts from internal interrupt controller */
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mfc0 t1,C0_SR
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nop
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and t1,t0
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mtc0 t1,C0_SR
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nop
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li t0,~SR_EXL /* Clear EXL in status register to allow memory exceptions to occur */
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mfc0 t1,C0_SR
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nop
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and t1,t0
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mtc0 t1,C0_SR
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nop
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#endif
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/*
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* Call the CPU model or BSP specific routine to decode the
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* interrupt source and actually vector to device ISR handlers.
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*/
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move a0,sp
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jal mips_vector_isr_handlers
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NOP
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/* Add the following code to disable interrupts (see DEBUG above) */
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#if 0
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li t0,SR_EXL /* Set EXL to hold off interrupts */
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mfc0 t1,C0_SR
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nop
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or t1,t0
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mtc0 t1,C0_SR
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nop
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li t0,CAUSE_IP2_MASK /* Enable interrupts from internal interrupt controller */
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mfc0 t1,C0_SR
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nop
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or t1,t0
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mtc0 t1,C0_SR
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nop
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#endif
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_ISR_Handler_cleanup:
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/*
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* --_ISR_Nest_level;
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*/
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lw t2,_ISR_Nest_level
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NOP
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add t2,t2,-1
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sw t2,_ISR_Nest_level
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/*
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* --_Thread_Dispatch_disable_level;
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*/
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lw t1,_Thread_Dispatch_disable_level
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NOP
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add t1,t1,-1
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sw t1,_Thread_Dispatch_disable_level
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/*
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* if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
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* goto the label "exit interrupt (simple case)"
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*/
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or t0,t2,t1
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bne t0,zero,_ISR_Handler_exit
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NOP
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/*
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* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
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* restore stack
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* #endif
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*
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* if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
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* goto the label "exit interrupt (simple case)"
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*/
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lw t0,_Context_Switch_necessary
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lw t1,_ISR_Signals_to_thread_executing
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NOP
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or t0,t0,t1
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beq t0,zero,_ISR_Handler_exit
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NOP
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/*
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** Turn on interrupts before entering Thread_Dispatch which
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** will run for a while, thus allowing new interrupts to
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** be serviced. Observe the Thread_Dispatch_disable_level interlock
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** that prevents recursive entry into Thread_Dispatch.
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*/
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mfc0 t0, C0_SR
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#if __mips == 3
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li t1,SR_EXL /* Clear EXL and Set IE to enable interrupts */
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not t1
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and t0,t1
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li t1,SR_IE
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#elif __mips == 1
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li t1,SR_IEC
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#endif
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or t0, t1
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mtc0 t0, C0_SR
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NOP
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/* save off our stack frame so the context switcher can get to it */
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la t0,__exceptionStackFrame
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STREG sp,(t0)
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jal _Thread_Dispatch
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NOP
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/* and make sure its clear in case we didn't dispatch. if we did, its
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** already cleared */
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la t0,__exceptionStackFrame
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STREG zero,(t0)
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NOP
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/*
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** turn interrupts back off while we restore context so
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** a badly timed interrupt won't accidentally mess things up
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*/
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mfc0 t0, C0_SR
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li t1,SR_IE /* Clear IE first (recommended) */
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not t1
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and t0,t1
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mtc0 t0, C0_SR
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li t1,SR_EXL | SR_IE /* Set EXL and IE, this puts status register bits back to interrupted state */
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or t0,t1
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mtc0 t0, C0_SR
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NOP
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/*
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* prepare to get out of interrupt
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* return from interrupt (maybe to _ISR_Dispatch)
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*
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* LABEL "exit interrupt (simple case):"
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* prepare to get out of interrupt
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* return from interrupt
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*/
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_ISR_Handler_exit:
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/* restore interrupt context from stack */
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LDREG t8, R_MDLO*R_SZ(sp)
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LDREG t0, R_T0*R_SZ(sp)
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mtlo t8
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LDREG t8, R_MDHI*R_SZ(sp)
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LDREG t1, R_T1*R_SZ(sp)
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mthi t8
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LDREG t2, R_T2*R_SZ(sp)
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LDREG t3, R_T3*R_SZ(sp)
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LDREG t4, R_T4*R_SZ(sp)
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LDREG t5, R_T5*R_SZ(sp)
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LDREG t6, R_T6*R_SZ(sp)
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LDREG t7, R_T7*R_SZ(sp)
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LDREG t8, R_T8*R_SZ(sp)
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LDREG t9, R_T9*R_SZ(sp)
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LDREG gp, R_GP*R_SZ(sp)
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LDREG fp, R_FP*R_SZ(sp)
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LDREG ra, R_RA*R_SZ(sp)
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LDREG a0, R_A0*R_SZ(sp)
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LDREG a1, R_A1*R_SZ(sp)
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LDREG a2, R_A2*R_SZ(sp)
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LDREG a3, R_A3*R_SZ(sp)
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LDREG v1, R_V1*R_SZ(sp)
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LDREG v0, R_V0*R_SZ(sp)
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LDREG k1, R_EPC*R_SZ(sp)
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mtc0 k1,C0_EPC
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.set noat
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LDREG AT, R_AT*R_SZ(sp)
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.set at
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ADDIU sp,sp,EXCP_STACK_SIZE
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_ISR_Handler_quick_exit:
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eret
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nop
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#if 0
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.global int7_isr
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.extern Interrupt_7_isr
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int7_isr:
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/* Verify interrupt is from Timer */
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la k0,IRCS /* read Interrupt Current Status register */
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lw k0,(k0)
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nop /* reading from external device */
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li k1,IRCS_CAUSE_MASK
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and k0,k0,k1 /* isolate interrupt cause */
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li k1,INT7INT /* test for interrupt 7 */
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subu k1,k0,k1
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beq k1,zero,int7_isr1
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nop
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j ra /* interrupt 7 no longer valid, return without doing anything */
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nop
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int7_isr1:
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j Interrupt_7_isr /* Jump to Interrupt 7 isr */
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nop
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#endif
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.set reorder
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ENDFRAME(rbtx4925_ISR_Handler)
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FRAME(_BRK_Handler,sp,0,ra)
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.set noreorder
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#ifdef USC
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la k0,INT_CFG3 /* Disable heartbeat interrupt in USC320, it interferes with PMON exception handler */
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lw k1,(k0)
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li k0,~HBI_MASK
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and k1,k1,k0
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la k0,INT_CFG3
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sw k1,(k0)
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#endif
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la k0,_brk_esr_link /* Jump to next exception handler in PMON exception chain */
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lw k0,(k0)
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lw k0,4(k0)
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j k0
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nop
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.set reorder
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ENDFRAME(_BRK_Handler)
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/**************************************************************************
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**
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** init_exc_vecs() - moves the exception code into the addresses
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** reserved for exception vectors
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**
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** UTLB Miss exception vector at address 0x80000000
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**
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** General exception vector at address 0x80000080
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**
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** RESET exception vector is at address 0xbfc00000
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**
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***************************************************************************/
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FRAME(init_exc_vecs,sp,0,ra)
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.set noreorder
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.extern mon_onintr
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/* Install interrupt handler in PMON exception handling chain */
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addiu sp,sp,-8
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sw ra,(sp) /* Save ra contents on stack */
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move a0,zero
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la a1,_int_esr_link
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jal mon_onintr /* Make PMON system call to install interrupt exception handler */
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nop
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li a0,9
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la a1,_brk_esr_link
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jal mon_onintr /* Make PMON system call to install break exception handler */
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nop
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lw ra,(sp)
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addiu sp,sp,8 /* Restore ra contents from stack */
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j ra
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nop
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.set reorder
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ENDFRAME(init_exc_vecs)
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#if 0 /* Unused code below */
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/*************************************************************
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* enable_int7(ints)
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* Enable interrupt 7
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*/
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FRAME(enable_int7,sp,0,ra)
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.set noreorder
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la t0,IRDM1 # Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
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li t1,0x0
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sw t1,(t0)
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la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2)
|
|
li t1,0x200
|
|
sw t1,(t0)
|
|
|
|
la t0,IRMSK # Set interrupt controller mask
|
|
li t1,0x0
|
|
sw t1,(t0)
|
|
|
|
la t0,IRDEN # Enable interrupts from controller
|
|
li t1,0x1
|
|
sw t1,(t0)
|
|
|
|
j ra
|
|
nop
|
|
.set reorder
|
|
ENDFRAME(enable_int7)
|
|
|
|
/*************************************************************
|
|
* disable_int7(ints)
|
|
* Disable interrupt 7
|
|
*/
|
|
FRAME(disable_int7,sp,0,ra)
|
|
.set noreorder
|
|
|
|
la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 0 to diasble int 7)
|
|
li t1,0x200
|
|
sw t1,(t0)
|
|
|
|
j ra
|
|
nop
|
|
.set reorder
|
|
ENDFRAME(disable_int7)
|
|
|
|
#endif
|
|
|
|
/*************************************************************
|
|
* tx4925exception:
|
|
* Diagnostic code that can be hooked to PMON interrupt handler.
|
|
* Generates pulse on PIO22 pin.
|
|
* Called from _exception code in PMON (see mips.s of PMON).
|
|
* Return address is located in k1.
|
|
*/
|
|
FRAME(tx4925exception,sp,0,ra)
|
|
.set noreorder
|
|
la k0,k1tmp
|
|
sw k1,(k0)
|
|
|
|
/* Activate TX4925 PIO22 signal for diagnostics */
|
|
lui k0,0xff1f
|
|
ori k0,k0,0xf500
|
|
lw k0,(k0)
|
|
lui k1,0x40
|
|
or k1,k1,k0
|
|
lui k0,0xff1f
|
|
ori k0,k0,0xf500
|
|
sw k1,(k0)
|
|
nop
|
|
|
|
/* De-activate TX4925 PIO22 signal for diagnostics */
|
|
lui k0,0xff1f
|
|
ori k0,k0,0xf500
|
|
lw k0,(k0)
|
|
lui k1,0x40
|
|
not k1
|
|
and k1,k1,k0
|
|
lui k0,0xff1f
|
|
ori k0,k0,0xf500
|
|
sw k1,(k0)
|
|
nop
|
|
|
|
la k0,k1tmp
|
|
lw k1,(k0)
|
|
j k1
|
|
.set reorder
|
|
ENDFRAME(tx4925exception)
|
|
|
|
|
|
|
|
|
|
.data
|
|
|
|
k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */
|
|
|
|
/*************************************************************
|
|
*
|
|
* Exception handler links, used in PMON exception handler chains
|
|
*/
|
|
/* Interrupt exception service routine link */
|
|
.global _int_esr_link
|
|
_int_esr_link:
|
|
.word 0
|
|
.word rbtx4925_ISR_Handler
|
|
|
|
/* Break exception service routine link */
|
|
.global _brk_esr_link
|
|
_brk_esr_link:
|
|
.word 0
|
|
.word _BRK_Handler
|
|
|
|
|
|
|
|
|