forked from Imagelibrary/rtems
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems/score/smpimpl.h>
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#include <libcpu/arm-cp15.h>
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#include <bsp/irq.h>
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static void bsp_inter_processor_interrupt(void *arg)
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{
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_SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
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}
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uint32_t _CPU_SMP_Initialize(void)
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{
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return arm_gic_irq_processor_count();
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}
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static rtems_interrupt_entry arm_a9mpcore_ipi_entry =
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RTEMS_INTERRUPT_ENTRY_INITIALIZER(
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bsp_inter_processor_interrupt,
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NULL,
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"IPI"
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);
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void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
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{
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if (cpu_count > 0) {
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rtems_status_code sc;
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sc = rtems_interrupt_entry_install(
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ARM_GIC_IRQ_SGI_0,
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RTEMS_INTERRUPT_UNIQUE,
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&arm_a9mpcore_ipi_entry
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);
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_Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL);
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#if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
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/* Enable unified L2 cache */
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rtems_cache_enable_data();
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#endif
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}
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}
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void _CPU_SMP_Prepare_start_multitasking( void )
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{
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/* Do nothing */
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}
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void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
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{
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arm_gic_irq_generate_software_irq(
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ARM_GIC_IRQ_SGI_0,
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1U << target_processor_index
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);
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}
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