forked from Imagelibrary/rtems
107 lines
2.5 KiB
C
107 lines
2.5 KiB
C
/*
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* Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp/bootcard.h>
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#include <bsp/fdt.h>
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#include <bsp/irq-generic.h>
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#include <bsp/linker-symbols.h>
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#include <bsp/alt_clock_manager.h>
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#include <libfdt.h>
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#ifdef BSP_FDT_IS_SUPPORTED
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uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
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{
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return intr[1] + 32;
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}
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static void set_clock(
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const void *fdt,
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int parent,
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ALT_CLK_t clk,
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const char *name
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)
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{
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int node;
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int len;
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const uint32_t *val;
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node = fdt_subnode_offset(fdt, parent, name);
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val = fdt_getprop(fdt, node, "clock-frequency", &len);
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if (val != NULL && len >= 4) {
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alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
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}
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}
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static void set_clock_by_output_name(
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const void *fdt,
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ALT_CLK_t clk,
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const char *clock_output_name
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)
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{
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int node;
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int len;
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const uint32_t *val;
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node = fdt_node_offset_by_prop_value(
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fdt,
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-1,
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"clock-output-names",
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clock_output_name,
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strlen(clock_output_name) + 1
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);
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val = fdt_getprop(fdt, node, "clock-frequency", &len);
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if (val != NULL && len >= 4) {
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alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
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}
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}
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static void update_clocks(void)
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{
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const void *fdt;
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int parent;
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fdt = bsp_fdt_get();
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/* Try to set by node name */
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parent = fdt_node_offset_by_compatible(fdt, -1, "altr,clk-mgr");
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parent = fdt_subnode_offset(fdt, parent, "clocks");
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set_clock(fdt, parent, ALT_CLK_OSC1, "osc1");
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set_clock(fdt, parent, ALT_CLK_IN_PIN_OSC2, "osc2");
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set_clock(fdt, parent, ALT_CLK_F2H_PERIPH_REF, "f2s_periph_ref_clk");
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set_clock(fdt, parent, ALT_CLK_F2H_SDRAM_REF, "f2s_sdram_ref_clk");
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/* Try to set by "clock-output-names" property value */
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set_clock_by_output_name(fdt, ALT_CLK_OSC1, "hps_0_eosc1-clk");
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set_clock_by_output_name(fdt, ALT_CLK_IN_PIN_OSC2, "hps_0_eosc2-clk");
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set_clock_by_output_name(fdt, ALT_CLK_F2H_PERIPH_REF, "hps_0_f2s_periph_ref_clk-clk");
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set_clock_by_output_name(fdt, ALT_CLK_F2H_SDRAM_REF, "hps_0_f2s_sdram_ref_clk-clk");
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}
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#endif
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void bsp_start(void)
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{
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#ifdef BSP_FDT_IS_SUPPORTED
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update_clocks();
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#endif
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bsp_interrupt_initialize();
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rtems_cache_coherent_add_area(
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bsp_section_nocacheheap_begin,
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(uintptr_t) bsp_section_nocacheheap_size
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);
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}
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