Sebastian Huber 3fe69b03a3 dev/serial: Optimize Zynq UART control reg writes ...

Just disable RX/TX to start the initialization sequence.  Do not double
disable RX/TX.  Enable RX/TX after the mode is set.

2024-09-17 01:53:58 +00:00

..

acpi

ACPICA: Add file for chosen ACPICA license

2024-08-06 21:28:15 +00:00

cache

bsps: Assign file to Doxygen group

2024-05-23 19:03:09 +00:00

dev

dev/serial: Optimize Zynq UART control reg writes

2024-09-17 01:53:58 +00:00

freebsd

bsps: Convert README to MarkDown

2024-08-05 21:37:42 +00:00

grlib

bsps: Avoid unused argument in clock interrupt

2024-03-20 16:34:09 +01:00

irq

rtems: Add get/set interrupt priorities

2024-05-10 13:26:22 +00:00

ofw

bsps/shared/ofw: Fix coverity defects

2021-05-06 16:44:38 -06:00

shmdr

bsps: Convert README to MarkDown

2024-08-05 21:37:42 +00:00

start

score: Disable ISR for fatal extensions

2024-08-23 14:54:37 +00:00

xil

Convert various files to README.md MarkDown

2024-08-02 21:13:35 +00:00

doxygen.h

doxygen: Add Doxygen files to a group

2023-02-16 08:27:09 +01:00

rtems-version.c

rtems: Add files to Doxygen groups

2023-07-26 07:18:29 +02:00