forked from Imagelibrary/rtems
1ef0afe60a
PR 1573/cpukit * cpu_asm.S, rtems/asm.h, rtems/score/cpu.h: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
226 lines
4.2 KiB
ArmAsm
226 lines
4.2 KiB
ArmAsm
/*
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* Hitachi H8 Score CPU functions
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* Copyright Comnet Technologies Ltd 1999
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*
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* Based on example code and other ports with this copyright:
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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;.equ RUNCONTEXT_ARG, er0
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;.equ HEIRCONTEXT_ARG, er1
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/*
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* Make sure we tell the assembler what type of CPU model we are
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* being compiled for.
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*/
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#if defined(__H8300H__)
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.h8300h
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#endif
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#if defined(__H8300S__)
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.h8300s
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#endif
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#if defined(__H8300SX__)
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.h8300sx
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#endif
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.text
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.text
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/*
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GCC Compiled with optimisations and Wimplicit decs to ensure
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that stack from doesn't change
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Supposedly R2 and R3 do not need to be saved but who knows
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Arg1 = er0 (not on stack)
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Arg2 = er1 (not on stack)
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*/
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.align 2
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.global SYM(_CPU_Context_switch)
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SYM(_CPU_Context_switch):
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/* Save Context */
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#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
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stc.w ccr,@(0:16,er0)
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mov.l er7,@(2:16,er0)
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mov.l er6,@(6:16,er0)
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mov.l er5,@(10:16,er0)
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mov.l er4,@(14:16,er0)
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mov.l er3,@(18:16,er0)
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mov.l er2,@(22:16,er0)
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/* Install New context */
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restore:
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mov.l @(22:16,er1),er2
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mov.l @(18:16,er1),er3
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mov.l @(14:16,er1),er4
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mov.l @(10:16,er1),er5
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mov.l @(6:16,er1),er6
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mov.l @(2:16,er1),er7
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ldc.w @(0:16,er1),ccr
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#endif
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rts
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.align 2
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.global SYM(_CPU_Context_restore)
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SYM(_CPU_Context_restore):
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#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
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mov.l er0,er1
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jmp @restore:24
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#endif
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/*
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VHandler for Vectored Interrupts
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All IRQ's are vectored to routine _ISR_#vector_number
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This routine stacks er0 and loads er0 with vector number
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before transferring to here
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*/
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.align 2
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.global SYM(_ISR_Handler)
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.extern SYM(_Vector_table)
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SYM(_ISR_Handler):
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#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
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mov.l er1,@-er7
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mov.l er2,@-er7
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mov.l er3,@-er7
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mov.l er4,@-er7
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mov.l er5,@-er7
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mov.l er6,@-er7
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/* Set IRQ Stack */
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orc #0xc0,ccr
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mov.l er7,er6 ; save stack pointer
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mov.l @ISR_NEST_LEVEL,er1
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bne nested
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mov.l @INTERRUPT_STACK_HIGH,er7
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nested:
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mov.l er6,@-er7 ; save sp so pop regardless of nest level
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;; Inc system counters
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mov.l @ISR_NEST_LEVEL,er1
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inc.l #1,er1
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mov.l er1,@ISR_NEST_LEVEL
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mov.l @SYM(_Thread_Dispatch_disable_level),er1
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inc.l #1,er1
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mov.l er1,@SYM(_Thread_Dispatch_disable_level)
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/* Vector to ISR */
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mov.l @SYM(_ISR_Vector_table),er1
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mov er0,er2 ; copy vector
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shll.l er2
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shll.l er2 ; vector = vector * 4 (sizeof(int))
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add.l er2,er1
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mov.l @er1,er1
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jsr @er1 ; er0 = arg1 =vector
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orc #0xc0,ccr
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mov.l @ISR_NEST_LEVEL,er1
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dec.l #1,er1
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mov.l er1,@ISR_NEST_LEVEL
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mov.l @SYM(_Thread_Dispatch_disable_level),er1
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dec.l #1,er1
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mov.l er1,@SYM(_Thread_Dispatch_disable_level)
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bne exit
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mov.b @DISPATCH_NEEDED,er1
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beq exit ; If no then exit
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/* Context switch here through ISR_Dispatch */
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bframe:
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orc #0xc0,ccr
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/* Pop Stack */
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mov @er7+,er6
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mov er6,er7
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/* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
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mov.l #0xc0000000,er2 /* Disable IRQ */
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or.l #SYM(_ISR_Dispatch),er2
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mov.l er2,@-er7
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rte
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/* Inner IRQ Return, pop flags and return */
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exit:
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/* Pop Stack */
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orc #0x80,ccr
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mov @er7+,er6
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mov er6,er7
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mov @er7+,er6
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mov @er7+,er5
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mov @er7+,er4
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mov @er7+,er3
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mov @er7+,er2
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mov @er7+,er1
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mov @er7+,er0
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#endif
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rte
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/*
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Called from ISR_Handler as a way of ending IRQ
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but allowing dispatch to another task.
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Must use RTE as CCR is still on stack but IRQ has been serviced.
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CCR and PC occupy same word so rte can be used.
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now using task stack
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*/
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.align 2
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.global SYM(_ISR_Dispatch)
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SYM(_ISR_Dispatch):
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#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
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jsr @SYM(_Thread_Dispatch)
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mov @er7+,er6
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mov @er7+,er5
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mov @er7+,er4
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mov @er7+,er3
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mov @er7+,er2
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mov @er7+,er1
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mov @er7+,er0
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#endif
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rte
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.align 2
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.global SYM(_CPU_Context_save_fp)
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SYM(_CPU_Context_save_fp):
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rts
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.align 2
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.global SYM(_CPU_Context_restore_fp)
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SYM(_CPU_Context_restore_fp):
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rts
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