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rtems/spec/build/bsps/dev/irq
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Sebastian Huber 5cc075712e irq/arm-gicv3.h: Customize CPU Interface init 
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers.  This fixes the build for the AArch32 target.

Add BSP options which define the initial values of CPU Interface registers.
2022-07-12 08:26:46 +02:00
..
objarmgicv3.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00
optarmgic-icc-bpr0.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00
optarmgic-icc-bpr1.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00
optarmgic-icc-ctrl.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00
optarmgic-icc-igrpen0.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00
optarmgic-icc-igrpen1.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00
optarmgic-icc-pmr.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00
optarmgic-icc-sre.yml
irq/arm-gicv3.h: Customize CPU Interface init
2022-07-12 08:26:46 +02:00