forked from Imagelibrary/rtems
201 lines
5.9 KiB
C
201 lines
5.9 KiB
C
/**
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* @file
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*
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* @ingroup mpc55xx
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*/
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/*
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* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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/*********************************************************************
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*
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* Copyright:
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* Freescale Semiconductor, INC. All Rights Reserved.
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* You are hereby granted a copyright license to use, modify, and
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* distribute the SOFTWARE so long as this entire notice is
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* retained without alteration in any modified and/or redistributed
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* versions, and that such modified versions are clearly identified
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* as such. No licenses are granted by implication, estoppel or
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* otherwise under any patents or trademarks of Freescale
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* Semiconductor, Inc. This software is provided on an "AS IS"
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* basis and without warranty.
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*
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* To the maximum extent permitted by applicable law, Freescale
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* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
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* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
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* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
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* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
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* AND ANY ACCOMPANYING WRITTEN MATERIALS.
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*
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* To the maximum extent permitted by applicable law, IN NO EVENT
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* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
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* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
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* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
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* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
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*
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* Freescale Semiconductor assumes no responsibility for the
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* maintenance and support of this software
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*
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********************************************************************/
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#ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
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#define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
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#include <stdint.h>
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#include <bspopts.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/****************************************************************************/
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/* MMU */
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/****************************************************************************/
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struct MMU_tag {
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union {
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uint32_t R;
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struct {
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uint32_t : 2;
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uint32_t TLBSEL : 2;
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uint32_t : 7;
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uint32_t ESEL : 5;
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uint32_t : 11;
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uint32_t NV : 5;
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} B;
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} MAS0;
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union {
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uint32_t R;
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struct {
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uint32_t VALID : 1;
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uint32_t IPROT : 1;
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uint32_t : 6;
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uint32_t TID : 8;
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uint32_t : 3;
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uint32_t TS : 1;
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uint32_t TSIZE : 5;
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uint32_t : 7;
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} B;
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} MAS1;
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union {
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uint32_t R;
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struct {
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uint32_t EPN : 22;
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uint32_t : 4;
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uint32_t VLE : 1;
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uint32_t W : 1;
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uint32_t I : 1;
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uint32_t M : 1;
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uint32_t G : 1;
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uint32_t E : 1;
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} B;
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} MAS2;
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union {
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uint32_t R;
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struct {
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uint32_t RPN : 22;
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uint32_t U0 : 1;
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uint32_t U1 : 1;
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uint32_t U2 : 1;
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uint32_t U3 : 1;
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uint32_t UX : 1;
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uint32_t SX : 1;
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uint32_t UW : 1;
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uint32_t SW : 1;
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uint32_t UR : 1;
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uint32_t SR : 1;
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} B;
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} MAS3;
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};
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union MMU_MAS4_tag {
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uint32_t R;
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struct {
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uint32_t : 2;
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uint32_t TLBSELD : 2;
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uint32_t : 10;
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uint32_t TIDSELD : 2;
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uint32_t : 4;
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uint32_t TSIZED : 4;
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uint32_t : 3;
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uint32_t WD : 1;
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uint32_t ID : 1;
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uint32_t MD : 1;
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uint32_t GD : 1;
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uint32_t ED : 1;
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} B;
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};
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union MMU_MAS6_tag {
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uint32_t R;
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struct {
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uint32_t : 8;
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uint32_t SPID : 8;
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uint32_t : 15;
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uint32_t SAS : 1;
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} B;
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};
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#define MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addreff, addrreal, size, x, w, r, io) \
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{ \
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.MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \
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.MAS1 = { .B = { \
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.VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \
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}, \
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.MAS2 = { .B = { \
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.EPN = (addreff) >> 10, .VLE = 0, \
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.W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \
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}, \
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.MAS3 = { .B = { \
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.RPN = (addrreal) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \
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.SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \
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} \
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}
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#define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \
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MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addr, addr, size, x, w, r, io)
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#define MPC55XX_MMU_1K 0
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#define MPC55XX_MMU_2K 1
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#define MPC55XX_MMU_4K 2
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#define MPC55XX_MMU_8K 3
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#define MPC55XX_MMU_16K 4
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#define MPC55XX_MMU_32K 5
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#define MPC55XX_MMU_64K 6
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#define MPC55XX_MMU_128K 7
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#define MPC55XX_MMU_256K 8
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#define MPC55XX_MMU_512K 9
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#define MPC55XX_MMU_1M 10
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#define MPC55XX_MMU_2M 11
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#define MPC55XX_MMU_4M 12
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#define MPC55XX_MMU_8M 13
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#define MPC55XX_MMU_16M 14
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#define MPC55XX_MMU_32M 15
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#define MPC55XX_MMU_64M 16
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#define MPC55XX_MMU_128M 17
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#define MPC55XX_MMU_256M 18
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#define MPC55XX_MMU_512M 19
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#define MPC55XX_MMU_1G 20
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#define MPC55XX_MMU_2G 21
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#define MPC55XX_MMU_4G 22
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */
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