forked from Imagelibrary/rtems
88 lines
2.9 KiB
Perl
88 lines
2.9 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-1999.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@chapter Board Support Packages
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@section Introduction
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An RTEMS Board Support Package (BSP) must be designed
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to support a particular processor and target board combination.
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This chapter presents a discussion of SPARC specific BSP issues.
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For more information on developing a BSP, refer to the chapter
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titled Board Support Packages in the RTEMS
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Applications User's Guide.
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@section System Reset
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An RTEMS based application is initiated or
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re-initiated when the SPARC processor is reset. When the SPARC
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is reset, the processor performs the following actions:
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@itemize @bullet
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@item the enable trap (ET) of the psr is set to 0 to disable
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traps,
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@item the supervisor bit (S) of the psr is set to 1 to enter
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supervisor mode, and
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@item the PC is set 0 and the nPC is set to 4.
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@end itemize
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The processor then begins to execute the code at
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location 0. It is important to note that all fields in the psr
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are not explicitly set by the above steps and all other
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registers retain their value from the previous execution mode.
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This is true even of the Trap Base Register (TBR) whose contents
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reflect the last trap which occurred before the reset.
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@section Processor Initialization
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It is the responsibility of the application's
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initialization code to initialize the TBR and install trap
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handlers for at least the register window overflow and register
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window underflow conditions. Traps should be enabled before
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invoking any subroutines to allow for register window
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management. However, interrupts should be disabled by setting
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the Processor Interrupt Level (pil) field of the psr to 15.
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RTEMS installs it's own Trap Table as part of initialization
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which is initialized with the contents of the Trap Table in
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place when the @code{rtems_initialize_executive} directive was invoked.
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Upon completion of executive initialization, interrupts are
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enabled.
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If this SPARC implementation supports on-chip caching
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and this is to be utilized, then it should be enabled during the
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reset application initialization code.
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In addition to the requirements described in the
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Board Support Packages chapter of the @value{LANGUAGE}
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Applications User's Manual for the reset code
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which is executed before the call to
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@code{rtems_initialize_executive}, the SPARC version has the following
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specific requirements:
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@itemize @bullet
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@item Must leave the S bit of the status register set so that
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the SPARC remains in the supervisor state.
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@item Must set stack pointer (sp) such that a minimum stack
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size of MINIMUM_STACK_SIZE bytes is provided for the
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@code{rtems_initialize_executive} directive.
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@item Must disable all external interrupts (i.e. set the pil
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to 15).
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@item Must enable traps so window overflow and underflow
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conditions can be properly handled.
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@item Must initialize the SPARC's initial trap table with at
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least trap handlers for register window overflow and register
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window underflow.
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@end itemize
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