forked from Imagelibrary/rtems
133 lines
2.8 KiB
C
133 lines
2.8 KiB
C
/**
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* @file
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*
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* @ingroup arm
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*
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* @brief ARM cache defines and implementation.
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*/
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/*
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* Copyright (c) 2009
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* D-82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#ifndef LIBCPU_ARM_CACHE_H
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#define LIBCPU_ARM_CACHE_H
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#ifdef __ARM_ARCH_5TEJ__
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#include <libcpu/arm-cp15.h>
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#define CPU_DATA_CACHE_ALIGNMENT 32
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#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
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static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
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{
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arm_cp15_data_cache_clean_line(d_addr);
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}
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static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
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{
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arm_cp15_data_cache_invalidate_line(d_addr);
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}
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static inline void _CPU_cache_freeze_data(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_unfreeze_data(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
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{
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arm_cp15_instruction_cache_invalidate_line(d_addr);
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}
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static inline void _CPU_cache_freeze_instruction(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_unfreeze_instruction(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_flush_entire_data(void)
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{
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arm_cp15_data_cache_test_and_clean();
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}
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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arm_cp15_data_cache_invalidate();
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}
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static inline void _CPU_cache_enable_data(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_disable(level);
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ctrl = arm_cp15_get_control();
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ctrl |= ARM_CP15_CTRL_C;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_disable_data(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_disable(level);
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ctrl = arm_cp15_get_control();
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ctrl &= ~ARM_CP15_CTRL_C;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_enable(level);
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arm_cp15_data_cache_test_and_clean_and_invalidate();
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void)
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{
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arm_cp15_instruction_cache_invalidate();
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}
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static inline void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_disable(level);
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ctrl = arm_cp15_get_control();
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ctrl |= ARM_CP15_CTRL_I;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_disable(level);
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ctrl = arm_cp15_get_control();
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ctrl &= ~ARM_CP15_CTRL_I;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_enable(level);
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}
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#endif
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#endif /* LIBCPU_ARM_CACHE_H */
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