forked from Imagelibrary/rtems
50539ba881
This support code is necessary for many Xilinx-provided bare metal device drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for all of these architectures is kept under bsps/include due to multiple architecture variants being supported which requires complex logic in the build system. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/xil/VERSION.
241 lines
5.7 KiB
C
241 lines
5.7 KiB
C
/******************************************************************************
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* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xpseudo_asm_gcc.h
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*
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* This header file contains macros for using inline assembler code. It is
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* written specifically for the GNU compiler.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- -------- -------- -----------------------------------------------
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* 5.00 pkp 05/21/14 First release
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* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
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* 7.2 asa 04/03/20 Renamed the str macro to strw.
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* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
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* </pre>
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*
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******************************************************************************/
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/**
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*@cond nocomments
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*/
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#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
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#define XPSEUDO_ASM_GCC_H /* by using protection macros */
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/***************************** Include Files ********************************/
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#include "xil_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/************************** Constant Definitions ****************************/
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/**************************** Type Definitions ******************************/
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/***************** Macros (Inline Functions) Definitions ********************/
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/* necessary for pre-processor */
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#define stringify(s) tostring(s)
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#define tostring(s) #s
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#if defined (__aarch64__)
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/* pseudo assembler instructions */
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#define mfcpsr() ({u32 rval = 0U; \
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asm volatile("mrs %0, DAIF" : "=r" (rval));\
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rval;\
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})
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#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
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#define cpsiei() //__asm__ __volatile__("cpsie i\n")
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#define cpsidi() //__asm__ __volatile__("cpsid i\n")
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#define cpsief() //__asm__ __volatile__("cpsie f\n")
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#define cpsidf() //__asm__ __volatile__("cpsid f\n")
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#define mtgpr(rn, v) /*__asm__ __volatile__(\
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"mov r" stringify(rn) ", %0 \n"\
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: : "r" (v)\
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)*/
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#define mfgpr(rn) /*({u32 rval; \
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__asm__ __volatile__(\
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"mov %0,r" stringify(rn) "\n"\
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: "=r" (rval)\
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);\
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rval;\
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})*/
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/* memory synchronization operations */
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/* Instruction Synchronization Barrier */
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#define isb() __asm__ __volatile__ ("isb sy")
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/* Data Synchronization Barrier */
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#define dsb() __asm__ __volatile__("dsb sy")
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/* Data Memory Barrier */
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#define dmb() __asm__ __volatile__("dmb sy")
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/* Memory Operations */
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#define ldr(adr) ({u64 rval; \
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__asm__ __volatile__(\
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"ldr %0,[%1]"\
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: "=r" (rval) : "r" (adr)\
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);\
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rval;\
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})
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#define mfelrel3() ({u64 rval = 0U; \
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asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
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rval;\
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})
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#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
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#else
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/* pseudo assembler instructions */
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#define mfcpsr() ({u32 rval = 0U; \
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__asm__ __volatile__(\
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"mrs %0, cpsr\n"\
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: "=r" (rval)\
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);\
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rval;\
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})
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#define mtcpsr(v) __asm__ __volatile__(\
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"msr cpsr,%0\n"\
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: : "r" (v) : "cc" \
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)
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#define cpsiei() __asm__ __volatile__("cpsie i\n")
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#define cpsidi() __asm__ __volatile__("cpsid i\n")
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#define cpsief() __asm__ __volatile__("cpsie f\n")
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#define cpsidf() __asm__ __volatile__("cpsid f\n")
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#define mtgpr(rn, v) __asm__ __volatile__(\
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"mov r" stringify(rn) ", %0 \n"\
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: : "r" (v)\
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)
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#define mfgpr(rn) ({u32 rval; \
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__asm__ __volatile__(\
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"mov %0,r" stringify(rn) "\n"\
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: "=r" (rval)\
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);\
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rval;\
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})
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/* memory synchronization operations */
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/* Instruction Synchronization Barrier */
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#define isb() __asm__ __volatile__ ("isb" : : : "memory")
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/* Data Synchronization Barrier */
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#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
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/* Data Memory Barrier */
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#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
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/* Memory Operations */
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#define ldr(adr) ({u32 rval; \
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__asm__ __volatile__(\
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"ldr %0,[%1]"\
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: "=r" (rval) : "r" (adr)\
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);\
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rval;\
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})
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#endif
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#define ldrb(adr) ({u8 rval; \
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__asm__ __volatile__(\
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"ldrb %0,[%1]"\
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: "=r" (rval) : "r" (adr)\
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);\
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rval;\
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})
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#define strw(adr, val) __asm__ __volatile__(\
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"str %0,[%1]\n"\
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: : "r" (val), "r" (adr)\
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)
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#define strb(adr, val) __asm__ __volatile__(\
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"strb %0,[%1]\n"\
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: : "r" (val), "r" (adr)\
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)
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/* Count leading zeroes (clz) */
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#define clz(arg) ({u8 rval; \
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__asm__ __volatile__(\
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"clz %0,%1"\
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: "=r" (rval) : "r" (arg)\
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);\
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rval;\
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})
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#if defined (__aarch64__)
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#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
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#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
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#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
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#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
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#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
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/* CP15 operations */
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#define mfcp(reg) ({u64 rval = 0U;\
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__asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
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rval;\
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})
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#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
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#else
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/* CP15 operations */
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#define mtcp(rn, v) __asm__ __volatile__(\
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"mcr " rn "\n"\
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: : "r" (v)\
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);
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#define mfcp(rn) ({u32 rval = 0U; \
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__asm__ __volatile__(\
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"mrc " rn "\n"\
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: "=r" (rval)\
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);\
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rval;\
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})
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#endif
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/************************** Variable Definitions ****************************/
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/************************** Function Prototypes *****************************/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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/**
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*@endcond
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*/
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#endif /* XPSEUDO_ASM_GCC_H */
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