forked from Imagelibrary/rtems
33f6e34b2d
This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
207 lines
7.1 KiB
C
207 lines
7.1 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* GRIOMMU Driver Interface
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*
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* COPYRIGHT (c) 2017
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* Cobham Gaisler AB
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* OVERVIEW
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* ========
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* This driver controls the GRIOMMU device located
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* at an on-chip AMBA.
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*/
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#ifndef __GRIOMMU_H__
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#define __GRIOMMU_H__
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#include <stdint.h>
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#include <stdio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void griommu_register_drv(void);
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#define GRIOMMU_ERR_OK 0
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#define GRIOMMU_ERR_NOINIT -1
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#define GRIOMMU_ERR_EINVAL -2
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#define GRIOMMU_ERR_IMPLEMENTED -3
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#define GRIOMMU_ERR_NOTFOUND -4
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/* Size of APV (has to be divided by page size in bytes) */
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#define GRIOMMU_APV_SIZE 0x20000000
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/* Alignment of APV */
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#define GRIOMMU_APV_ALIGN 0x10
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/* IOMMU APV allocation helper functions */
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extern void * griommu_apv_new(void);
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extern void griommu_apv_delete(void * apv);
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/* IOMMU Master Setup */
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/* IOMMU Master find */
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/*
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* GRIOMMU MASTER register fields
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*/
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#define MASTER_VENDOR (0xff << MASTER_VENDOR_BIT)
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#define MASTER_DEVICE (0xfff << MASTER_DEVICE_BIT)
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#define MASTER_BS (0x1 << MASTER_BS_BIT)
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#define MASTER_GROUP (0xf << MASTER_GROUP_BIT)
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#define MASTER_VENDOR_BIT 24
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#define MASTER_DEVICE_BIT 12
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#define MASTER_BS_BIT 4
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#define MASTER_GROUP_BIT 0
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#define GRIOMMU_OPTIONS_BUS0 0
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#define GRIOMMU_OPTIONS_BUS1 1
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extern int griommu_master_setup(int master, int group, int options);
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extern int griommu_master_find(int vendor, int device, int instance);
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extern int griommu_master_info(int master, uint32_t * info);
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#define griommu_get_master_vendor(info) \
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((info & MASTER_VENDOR) >> MASTER_VENDOR_BIT)
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#define griommu_get_master_device(info) \
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((info & MASTER_DEVICE) >> MASTER_DEVICE_BIT)
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#define griommu_get_master_routing(info) \
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((info & MASTER_BS) >> MASTER_BS_BIT)
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#define griommu_get_master_group(info) \
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((info & MASTER_GROUP) >> MASTER_GROUP_BIT)
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/* IOMMU Group Setup */
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#define GRIOMMU_OPTIONS_GROUP_PASSTHROUGH 2
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#define GRIOMMU_OPTIONS_GROUP_ENABLE 1
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#define GRIOMMU_OPTIONS_GROUP_DISABLE 0
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extern int griommu_group_setup(int group, void * apv, int options);
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extern int griommu_group_info(int group, uint32_t * info);
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#define GRIOMMU_OPTIONS_APV_ALLOW 0x1
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#define GRIOMMU_OPTIONS_APV_DONTALLOW 0x0
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extern int griommu_group_apv_init(int group, int options);
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extern int griommu_group_apv_address_set(int group, uint32_t addr, int size,
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int options);
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extern int griommu_group_apv_page_set(int group, int index, int size,
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int options);
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extern int griommu_group_apv_flush(int group);
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/* IOMMU Setup */
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/*
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* GRIOMMU CTRL register fields
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*/
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#define CTRL_PGSZ (0x7 << CTRL_PGSZ_BIT)
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#define CTRL_LB (0x1 << CTRL_LB_BIT)
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#define CTRL_SP (0x1 << CTRL_SP_BIT)
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#define CTRL_ITR (0xf << CTRL_ITR_BIT)
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#define CTRL_DP (0x1 << CTRL_DP_BIT)
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#define CTRL_SIV (0x1 << CTRL_SIV_BIT)
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#define CTRL_HPROT (0x3 << CTRL_HPROT_BIT)
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#define CTRL_AU (0x1 << CTRL_AU_BIT)
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#define CTRL_WP (0x1 << CTRL_WP_BIT)
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#define CTRL_DM (0x1 << CTRL_DM_BIT)
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#define CTRL_GS (0x1 << CTRL_GS_BIT)
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#define CTRL_CE (0x1 << CTRL_CE_BIT)
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#define CTRL_PM (0x3 << CTRL_PM_BIT)
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#define CTRL_PM_APV (0x0 << CTRL_PM_BIT)
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#define CTRL_PM_IOMMU (0x1 << CTRL_PM_BIT)
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#define CTRL_EN (0x1 << CTRL_EN_BIT)
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#define CTRL_PGSZ_BIT 18
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#define CTRL_LB_BIT 17
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#define CTRL_SP_BIT 16
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#define CTRL_ITR_BIT 12
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#define CTRL_DP_BIT 11
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#define CTRL_SIV_BIT 10
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#define CTRL_HPROT_BIT 8
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#define CTRL_AU_BIT 7
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#define CTRL_WP_BIT 6
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#define CTRL_DM_BIT 5
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#define CTRL_GS_BIT 4
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#define CTRL_CE_BIT 3
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#define CTRL_PM_BIT 1
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#define CTRL_EN_BIT 0
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#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0
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#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB
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#define GRIOMMU_OPTIONS_CACHE_DISABLE 0
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#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE
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#define GRIOMMU_OPTIONS_GROUPADDRESSING_DISABLE 0
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#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS
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#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0
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#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP
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#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0
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#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU
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#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP
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#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0
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#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0
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#define GRIOMMU_OPTIONS_PAGESIZE_8KIB (0x1 << CTRL_PGSZ_BIT)
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#define GRIOMMU_OPTIONS_PAGESIZE_16KIB (0x2 << CTRL_PGSZ_BIT)
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#define GRIOMMU_OPTIONS_PAGESIZE_32KIB (0x3 << CTRL_PGSZ_BIT)
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#define GRIOMMU_OPTIONS_PAGESIZE_64KIB (0x4 << CTRL_PGSZ_BIT)
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#define GRIOMMU_OPTIONS_PAGESIZE_128KIB (0x5 << CTRL_PGSZ_BIT)
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#define GRIOMMU_OPTIONS_PAGESIZE_256KIB (0x6 << CTRL_PGSZ_BIT)
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#define GRIOMMU_OPTIONS_PAGESIZE_512KIB (0x7 << CTRL_PGSZ_BIT)
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extern int griommu_setup(int options);
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extern int griommu_status(void);
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#define GRIOMMU_MODE_IOMMU 1
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#define GRIOMMU_MODE_GROUPAPV 0
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extern int griommu_enable(int mode);
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extern int griommu_disable(void);
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/* IOMMU APV setup */
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extern int griommu_apv_flush(void);
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extern int griommu_apv_init(void * apv, int options);
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extern int griommu_apv_address_set(void * apv, uint32_t addr, int size,
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int options);
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extern int griommu_apv_page_set(void * apv, int index, int size, int options);
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/* GRIOMMU Interrupts */
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/* Function Interrupt-Code ISR callback prototype.
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* arg - Custom arg provided by user
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* access - AHB Access that failed
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* status - Error status register of the GRIOMMU core
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*/
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typedef void (*griommu_isr_t)(void *arg, uint32_t access, uint32_t status);
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#define GRIOMMU_INTERRUPT_ALL (0x2f << 0)
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#define GRIOMMU_INTERRUPT_PARITY_ERROR (0x1 << 5)
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#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED (0x1 << 3)
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#define GRIOMMU_INTERRUPT_FLUSH_START (0x1 << 2)
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#define GRIOMMU_INTERRUPT_ACCESS_DENIED (0x1 << 1)
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#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR (0x1 << 0)
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extern int griommu_isr_register(griommu_isr_t isr, void * arg, int options);
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extern int griommu_isr_unregister(void);
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extern int griommu_interrupt_unmask(int options);
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extern int griommu_interrupt_mask(int options);
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extern int griommu_error_status(uint32_t * access);
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extern int griommu_print(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __GRIOMMU_H__ */
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