forked from Imagelibrary/rtems
447 lines
12 KiB
C
447 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSDeviceGRETHGBIT
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*
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* @brief This header file defines the GRETH_GBIT register block interface.
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*/
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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/* Generated from spec:/dev/grlib/if/grethgbit-header */
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#ifndef _GRLIB_GRETHGBIT_REGS_H
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#define _GRLIB_GRETHGBIT_REGS_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Generated from spec:/dev/grlib/if/grethgbit */
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/**
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* @defgroup RTEMSDeviceGRETHGBIT GRETH_GBIT
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*
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* @ingroup RTEMSDeviceGRLIB
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*
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* @brief This group contains the GRETH_GBIT interfaces.
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*
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* @{
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*/
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/**
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* @defgroup RTEMSDeviceGRETHGBITCR control register (CR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_CR_EA 0x80000000U
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#define GRETHGBIT_CR_BS_SHIFT 28
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#define GRETHGBIT_CR_BS_MASK 0x70000000U
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#define GRETHGBIT_CR_BS_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> \
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GRETHGBIT_CR_BS_SHIFT )
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#define GRETHGBIT_CR_BS_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_CR_BS_MASK ) | \
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( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
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GRETHGBIT_CR_BS_MASK ) )
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#define GRETHGBIT_CR_BS( _val ) \
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( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
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GRETHGBIT_CR_BS_MASK )
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#define GRETHGBIT_CR_GA 0x8000000U
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#define GRETHGBIT_CR_MA 0x4000000U
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#define GRETHGBIT_CR_MC 0x2000000U
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#define GRETHGBIT_CR_ED 0x4000U
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#define GRETHGBIT_CR_RD 0x2000U
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#define GRETHGBIT_CR_DD 0x1000U
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#define GRETHGBIT_CR_ME 0x800U
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#define GRETHGBIT_CR_PI 0x400U
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#define GRETHGBIT_CR_BM 0x200U
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#define GRETHGBIT_CR_GB 0x100U
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#define GRETHGBIT_CR_SP 0x80U
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#define GRETHGBIT_CR_RS 0x40U
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#define GRETHGBIT_CR_PM 0x20U
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#define GRETHGBIT_CR_FD 0x10U
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#define GRETHGBIT_CR_RI 0x8U
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#define GRETHGBIT_CR_TI 0x4U
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#define GRETHGBIT_CR_RE 0x2U
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#define GRETHGBIT_CR_TE 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITSR status register. (SR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_SR_PS 0x100U
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#define GRETHGBIT_SR_IA 0x80U
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#define GRETHGBIT_SR_TS 0x40U
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#define GRETHGBIT_SR_TA 0x20U
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#define GRETHGBIT_SR_RA 0x10U
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#define GRETHGBIT_SR_TI 0x8U
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#define GRETHGBIT_SR_RI 0x4U
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#define GRETHGBIT_SR_TE 0x2U
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#define GRETHGBIT_SR_RE 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITMACMSB MAC address MSB. (MACMSB)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_MACMSB_MSB_SHIFT 0
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#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU
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#define GRETHGBIT_MACMSB_MSB_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> \
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GRETHGBIT_MACMSB_MSB_SHIFT )
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#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \
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( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
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GRETHGBIT_MACMSB_MSB_MASK ) )
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#define GRETHGBIT_MACMSB_MSB( _val ) \
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( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
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GRETHGBIT_MACMSB_MSB_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITMACLSB MAC address LSB. (MACLSB)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_MACLSB_LSB_SHIFT 0
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#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU
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#define GRETHGBIT_MACLSB_LSB_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> \
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GRETHGBIT_MACLSB_LSB_SHIFT )
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#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \
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( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
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GRETHGBIT_MACLSB_LSB_MASK ) )
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#define GRETHGBIT_MACLSB_LSB( _val ) \
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( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
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GRETHGBIT_MACLSB_LSB_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITMDIO MDIO control/status register. (MDIO)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_MDIO_DATA_SHIFT 16
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#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U
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#define GRETHGBIT_MDIO_DATA_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> \
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GRETHGBIT_MDIO_DATA_SHIFT )
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#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \
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( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
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GRETHGBIT_MDIO_DATA_MASK ) )
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#define GRETHGBIT_MDIO_DATA( _val ) \
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( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
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GRETHGBIT_MDIO_DATA_MASK )
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#define GRETHGBIT_MDIO_PHYADDR_SHIFT 11
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#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U
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#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_MDIO_PHYADDR_MASK ) >> \
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GRETHGBIT_MDIO_PHYADDR_SHIFT )
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#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \
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( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
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GRETHGBIT_MDIO_PHYADDR_MASK ) )
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#define GRETHGBIT_MDIO_PHYADDR( _val ) \
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( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
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GRETHGBIT_MDIO_PHYADDR_MASK )
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#define GRETHGBIT_MDIO_REGADDR_SHIFT 6
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#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U
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#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_MDIO_REGADDR_MASK ) >> \
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GRETHGBIT_MDIO_REGADDR_SHIFT )
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#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \
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( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
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GRETHGBIT_MDIO_REGADDR_MASK ) )
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#define GRETHGBIT_MDIO_REGADDR( _val ) \
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( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
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GRETHGBIT_MDIO_REGADDR_MASK )
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#define GRETHGBIT_MDIO_BU 0x8U
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#define GRETHGBIT_MDIO_LF 0x4U
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#define GRETHGBIT_MDIO_RD 0x2U
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#define GRETHGBIT_MDIO_WR 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITTDTBA \
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* transmitter descriptor table base address register. (TDTBA)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10
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#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U
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#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_TDTBA_BASEADDR_MASK ) >> \
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GRETHGBIT_TDTBA_BASEADDR_SHIFT )
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#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \
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( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
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GRETHGBIT_TDTBA_BASEADDR_MASK ) )
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#define GRETHGBIT_TDTBA_BASEADDR( _val ) \
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( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
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GRETHGBIT_TDTBA_BASEADDR_MASK )
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#define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3
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#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U
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#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_TDTBA_DESCPNT_MASK ) >> \
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GRETHGBIT_TDTBA_DESCPNT_SHIFT )
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#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \
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( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
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GRETHGBIT_TDTBA_DESCPNT_MASK ) )
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#define GRETHGBIT_TDTBA_DESCPNT( _val ) \
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( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
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GRETHGBIT_TDTBA_DESCPNT_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITRDTBA \
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* receiver descriptor table base address register. (RDTBA)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10
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#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U
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#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_RDTBA_BASEADDR_MASK ) >> \
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GRETHGBIT_RDTBA_BASEADDR_SHIFT )
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#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \
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( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
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GRETHGBIT_RDTBA_BASEADDR_MASK ) )
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#define GRETHGBIT_RDTBA_BASEADDR( _val ) \
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( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
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GRETHGBIT_RDTBA_BASEADDR_MASK )
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#define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3
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#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U
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#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_RDTBA_DESCPNT_MASK ) >> \
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GRETHGBIT_RDTBA_DESCPNT_SHIFT )
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#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \
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( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
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GRETHGBIT_RDTBA_DESCPNT_MASK ) )
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#define GRETHGBIT_RDTBA_DESCPNT( _val ) \
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( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
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GRETHGBIT_RDTBA_DESCPNT_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITEDCLMACMSB EDCL MAC address MSB. (EDCLMACMSB)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0
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#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU
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#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_EDCLMACMSB_MSB_MASK ) >> \
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GRETHGBIT_EDCLMACMSB_MSB_SHIFT )
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#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \
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( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
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GRETHGBIT_EDCLMACMSB_MSB_MASK ) )
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#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \
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( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
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GRETHGBIT_EDCLMACMSB_MSB_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRETHGBITEDCLMACLSB EDCL MAC address LSB. (EDCLMACLSB)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0
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#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU
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#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \
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( ( ( _reg ) & GRETHGBIT_EDCLMACLSB_LSB_MASK ) >> \
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GRETHGBIT_EDCLMACLSB_LSB_SHIFT )
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#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \
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( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
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GRETHGBIT_EDCLMACLSB_LSB_MASK ) )
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#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \
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( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
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GRETHGBIT_EDCLMACLSB_LSB_MASK )
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/** @} */
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/**
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* @brief This structure defines the GRETH_GBIT register block memory map.
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*/
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typedef struct grethgbit {
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITCR.
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*/
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uint32_t cr;
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITSR.
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*/
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uint32_t sr;
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITMACMSB.
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*/
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uint32_t macmsb;
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITMACLSB.
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*/
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uint32_t maclsb;
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITMDIO.
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*/
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uint32_t mdio;
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITTDTBA.
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*/
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uint32_t tdtba;
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITRDTBA.
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*/
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uint32_t rdtba;
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uint32_t reserved_1c_28[ 3 ];
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITEDCLMACMSB.
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*/
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uint32_t edclmacmsb;
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/**
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* @brief See @ref RTEMSDeviceGRETHGBITEDCLMACLSB.
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*/
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uint32_t edclmaclsb;
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} grethgbit;
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _GRLIB_GRETHGBIT_REGS_H */
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